Commit 2dee50ab authored by Ralph Siemsen's avatar Ralph Siemsen Committed by Geert Uytterhoeven
Browse files

clk: renesas: r9a06g032: Fix UART clkgrp bitsel 



There are two UART clock groups, each having a mux to select its
upstream clock source. The register/bit definitions for accessing these
two muxes appear to have been reversed since introduction. Correct them
so as to match the hardware manual.

Fixes: 4c3d8852 ("clk: renesas: Renesas R9A06G032 clock driver")

Signed-off-by: default avatarRalph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: default avatarPhil Edworthy <phil.edworthy@renesas.com>
Link: https://lore.kernel.org/r/20220518182527.1693156-1-ralph.siemsen@linaro.org


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent f46efcc4

drivers/clk/renesas/r9a06g032-clocks.c

+4 −4
Original line number Diff line number Diff line
@@ -288,8 +288,8 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] = { 
		.name = "uart_group_012",

		.type = K_BITSEL,

		.source = 1 + R9A06G032_DIV_UART,

		/* R9A06G032_SYSCTRL_REG_PWRCTRL_PG1_PR2 */

		.dual.sel = ((0xec / 4) << 5) | 24,

		/* R9A06G032_SYSCTRL_REG_PWRCTRL_PG0_0 */

		.dual.sel = ((0x34 / 4) << 5) | 30,

		.dual.group = 0,

	},

	{
@@ -297,8 +297,8 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] = { 
		.name = "uart_group_34567",

		.type = K_BITSEL,

		.source = 1 + R9A06G032_DIV_P2_PG,

		/* R9A06G032_SYSCTRL_REG_PWRCTRL_PG0_0 */

		.dual.sel = ((0x34 / 4) << 5) | 30,

		/* R9A06G032_SYSCTRL_REG_PWRCTRL_PG1_PR2 */

		.dual.sel = ((0xec / 4) << 5) | 24,

		.dual.group = 1,

	},

	D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0x1b2, 0x1b3, 0x1b4, 0x1b5),