Commit 2db16c6e authored by Mirela Rabulea's avatar Mirela Rabulea Committed by Mauro Carvalho Chehab
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media: imx-jpeg: Add V4L2 driver for i.MX8 JPEG Encoder/Decoder 



V4L2 driver for the JPEG encoder/decoder from i.MX8QXP/i.MX8QM application
processors.
The multi-planar buffers API is used.

Baseline and extended sequential jpeg decoding is supported.
Progressive jpeg decoding is not supported by the IP.
Supports encode and decode of various formats:
     YUV444, YUV422, YUV420, RGB, ARGB, Gray
YUV420 is the only multi-planar format supported.
Minimum resolution is 64 x 64, maximum 8192 x 8192.
The alignment requirements for the resolution depend on the format,
multiple of 16 resolutions should work for all formats.

v4l2-compliance tests are passing, including the
streaming tests, "v4l2-compliance -s"

[hverkuil: fix kernel-doc typos]

Signed-off-by: default avatarMirela Rabulea <mirela.rabulea@nxp.com>
Signed-off-by: default avatarHans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+huawei@kernel.org>
parent 819f3ea5

drivers/media/platform/Kconfig

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@@ -253,6 +253,8 @@ config VIDEO_IMX_PXP 
	  The i.MX Pixel Pipeline is a memory-to-memory engine for scaling,

	  color space conversion, and rotation.



source "drivers/media/platform/imx-jpeg/Kconfig"



config VIDEO_MEDIATEK_JPEG

	tristate "Mediatek JPEG Codec driver"

	depends on MTK_IOMMU_V1 || MTK_IOMMU || COMPILE_TEST

drivers/media/platform/Makefile

+1 −0
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@@ -21,6 +21,7 @@ obj-$(CONFIG_VIDEO_MX2_EMMAPRP) += mx2_emmaprp.o 
obj-$(CONFIG_VIDEO_CODA)		+= coda/



obj-$(CONFIG_VIDEO_IMX_PXP)		+= imx-pxp.o

obj-$(CONFIG_VIDEO_IMX8_JPEG)		+= imx-jpeg/



obj-$(CONFIG_VIDEO_MEM2MEM_DEINTERLACE)	+= m2m-deinterlace.o

drivers/media/platform/imx-jpeg/Kconfig

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# SPDX-License-Identifier: GPL-2.0

config VIDEO_IMX8_JPEG

	tristate "IMX8 JPEG Encoder/Decoder"

	depends on VIDEO_DEV && VIDEO_V4L2

	select VIDEOBUF2_DMA_CONTIG

	select V4L2_MEM2MEM_DEV

	select V4L2_JPEG_HELPER

	default m

	help

	  This is a video4linux2 driver for the i.MX8 QXP/QM integrated

	  JPEG encoder/decoder.

drivers/media/platform/imx-jpeg/Makefile

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# SPDX-License-Identifier: GPL-2.0

mxc-jpeg-encdec-objs := mxc-jpeg-hw.o mxc-jpeg.o

obj-$(CONFIG_VIDEO_IMX8_JPEG) += mxc-jpeg-encdec.o

drivers/media/platform/imx-jpeg/mxc-jpeg-hw.c

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// SPDX-License-Identifier: GPL-2.0

/*

 * i.MX8QXP/i.MX8QM JPEG encoder/decoder v4l2 driver

 *

 * Copyright 2018-2019 NXP

 */



#include <linux/delay.h>

#include <media/videobuf2-core.h>

#include "mxc-jpeg-hw.h"



#define print_wrapper_reg(dev, base_address, reg_offset)\

		internal_print_wrapper_reg(dev, (base_address), #reg_offset,\

					   (reg_offset))

#define internal_print_wrapper_reg(dev, base_address, reg_name, reg_offset) {\

		int val;\

		val = readl((base_address) + (reg_offset));\

		dev_dbg(dev, "Wrapper reg %s = 0x%x\n", reg_name, val);\

}



void print_descriptor_info(struct device *dev, struct mxc_jpeg_desc *desc)

{

	dev_dbg(dev, " MXC JPEG NEXT_DESCPT_PTR 0x%x\n",

		desc->next_descpt_ptr);

	dev_dbg(dev, " MXC JPEG BUF_BASE0 0x%x\n", desc->buf_base0);

	dev_dbg(dev, " MXC JPEG BUF_BASE1 0x%x\n", desc->buf_base1);

	dev_dbg(dev, " MXC JPEG LINE_PITCH %d\n", desc->line_pitch);

	dev_dbg(dev, " MXC JPEG STM_BUFBASE 0x%x\n", desc->stm_bufbase);

	dev_dbg(dev, " MXC JPEG STM_BUFSIZE %d\n", desc->stm_bufsize);

	dev_dbg(dev, " MXC JPEG IMGSIZE %x (%d x %d)\n", desc->imgsize,

		desc->imgsize >> 16, desc->imgsize & 0xFFFF);

	dev_dbg(dev, " MXC JPEG STM_CTRL 0x%x\n", desc->stm_ctrl);

}



void print_cast_status(struct device *dev, void __iomem *reg,

		       unsigned int mode)

{

	dev_dbg(dev, "CAST IP status regs:\n");

	print_wrapper_reg(dev, reg, CAST_STATUS0);

	print_wrapper_reg(dev, reg, CAST_STATUS1);

	print_wrapper_reg(dev, reg, CAST_STATUS2);

	print_wrapper_reg(dev, reg, CAST_STATUS3);

	print_wrapper_reg(dev, reg, CAST_STATUS4);

	print_wrapper_reg(dev, reg, CAST_STATUS5);

	print_wrapper_reg(dev, reg, CAST_STATUS6);

	print_wrapper_reg(dev, reg, CAST_STATUS7);

	print_wrapper_reg(dev, reg, CAST_STATUS8);

	print_wrapper_reg(dev, reg, CAST_STATUS9);

	print_wrapper_reg(dev, reg, CAST_STATUS10);

	print_wrapper_reg(dev, reg, CAST_STATUS11);

	print_wrapper_reg(dev, reg, CAST_STATUS12);

	print_wrapper_reg(dev, reg, CAST_STATUS13);

	if (mode == MXC_JPEG_DECODE)

		return;

	print_wrapper_reg(dev, reg, CAST_STATUS14);

	print_wrapper_reg(dev, reg, CAST_STATUS15);

	print_wrapper_reg(dev, reg, CAST_STATUS16);

	print_wrapper_reg(dev, reg, CAST_STATUS17);

	print_wrapper_reg(dev, reg, CAST_STATUS18);

	print_wrapper_reg(dev, reg, CAST_STATUS19);

}



void print_wrapper_info(struct device *dev, void __iomem *reg)

{

	dev_dbg(dev, "Wrapper regs:\n");

	print_wrapper_reg(dev, reg, GLB_CTRL);

	print_wrapper_reg(dev, reg, COM_STATUS);

	print_wrapper_reg(dev, reg, BUF_BASE0);

	print_wrapper_reg(dev, reg, BUF_BASE1);

	print_wrapper_reg(dev, reg, LINE_PITCH);

	print_wrapper_reg(dev, reg, STM_BUFBASE);

	print_wrapper_reg(dev, reg, STM_BUFSIZE);

	print_wrapper_reg(dev, reg, IMGSIZE);

	print_wrapper_reg(dev, reg, STM_CTRL);

}



void mxc_jpeg_enable_irq(void __iomem *reg, int slot)

{

	writel(0xFFFFFFFF, reg + MXC_SLOT_OFFSET(slot, SLOT_IRQ_EN));

}



void mxc_jpeg_sw_reset(void __iomem *reg)

{

	/*

	 * engine soft reset, internal state machine reset

	 * this will not reset registers, however, it seems

	 * the registers may remain inconsistent with the internal state

	 * so, on purpose, at least let GLB_CTRL bits clear after this reset

	 */

	writel(GLB_CTRL_SFT_RST, reg + GLB_CTRL);

}



void mxc_jpeg_enc_mode_conf(struct device *dev, void __iomem *reg)

{

	dev_dbg(dev, "CAST Encoder CONFIG...\n");

	/*

	 * "Config_Mode" enabled, "Config_Mode auto clear enabled",

	 */

	writel(0xa0, reg + CAST_MODE);



	/* all markers and segments */

	writel(0x3ff, reg + CAST_CFG_MODE);



	/* quality factor */

	writel(0x4b, reg + CAST_QUALITY);

}



void mxc_jpeg_enc_mode_go(struct device *dev, void __iomem *reg)

{

	dev_dbg(dev, "CAST Encoder GO...\n");

	/*

	 * "GO" enabled, "GO bit auto clear" enabled

	 */

	writel(0x140, reg + CAST_MODE);

}



void mxc_jpeg_dec_mode_go(struct device *dev, void __iomem *reg)

{

	dev_dbg(dev, "CAST Decoder GO...\n");

	writel(MXC_DEC_EXIT_IDLE_MODE, reg + CAST_CTRL);

}



int mxc_jpeg_enable(void __iomem *reg)

{

	u32 regval;



	writel(GLB_CTRL_JPG_EN, reg + GLB_CTRL);

	regval = readl(reg);

	return regval;

}



void mxc_jpeg_enable_slot(void __iomem *reg, int slot)

{

	u32 regval;



	regval = readl(reg + GLB_CTRL);

	writel(GLB_CTRL_SLOT_EN(slot) | regval, reg + GLB_CTRL);

}



void mxc_jpeg_set_l_endian(void __iomem *reg, int le)

{

	u32 regval;



	regval = readl(reg + GLB_CTRL);

	regval &= ~GLB_CTRL_L_ENDIAN(1); /* clear */

	writel(GLB_CTRL_L_ENDIAN(le) | regval, reg + GLB_CTRL); /* set */

}



void mxc_jpeg_set_bufsize(struct mxc_jpeg_desc *desc,  u32 bufsize)

{

	desc->stm_bufsize = bufsize;

}



void mxc_jpeg_set_res(struct mxc_jpeg_desc *desc, u16 w, u16 h)

{

	desc->imgsize = w << 16 | h;

}



void mxc_jpeg_set_line_pitch(struct mxc_jpeg_desc *desc, u32 line_pitch)

{

	desc->line_pitch = line_pitch;

}



void mxc_jpeg_set_desc(u32 desc, void __iomem *reg, int slot)

{

	writel(desc | MXC_NXT_DESCPT_EN,

	       reg + MXC_SLOT_OFFSET(slot, SLOT_NXT_DESCPT_PTR));

}