Commit 2da37761 authored by Christophe Leroy's avatar Christophe Leroy Committed by Michael Ellerman
Browse files

powerpc/32: Fix objtool unannotated intra-function call warnings 



Fix several annotations in assembly files on PPC32.

[Sathvika Vasireddy: Changed subject line and removed Kconfig change to
 enable objtool, as it is a part of "objtool/powerpc: Enable objtool to
 be built on ppc" patch in this series.]

Tested-by: default avatarNaveen N. Rao <naveen.n.rao@linux.vnet.ibm.com>
Reviewed-by: default avatarNaveen N. Rao <naveen.n.rao@linux.vnet.ibm.com>
Acked-by: default avatarJosh Poimboeuf <jpoimboe@kernel.org>
Signed-off-by: default avatarChristophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: default avatarSathvika Vasireddy <sv@linux.ibm.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20221114175754.1131267-7-sv@linux.ibm.com
parent 1c137323

arch/powerpc/kernel/cpu_setup_6xx.S

+18 −8
Original line number Diff line number Diff line
@@ -4,6 +4,8 @@ 
 *    Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)

 */



#include <linux/linkage.h>



#include <asm/processor.h>

#include <asm/page.h>

#include <asm/cputable.h>
@@ -81,7 +83,7 @@ _GLOBAL(__setup_cpu_745x) 
	blr



/* Enable caches for 603's, 604, 750 & 7400 */

setup_common_caches:

SYM_FUNC_START_LOCAL(setup_common_caches)

	mfspr	r11,SPRN_HID0

	andi.	r0,r11,HID0_DCE

	ori	r11,r11,HID0_ICE|HID0_DCE
@@ -95,11 +97,12 @@ setup_common_caches: 
	sync

	isync

	blr

SYM_FUNC_END(setup_common_caches)



/* 604, 604e, 604ev, ...

 * Enable superscalar execution & branch history table

 */

setup_604_hid0:

SYM_FUNC_START_LOCAL(setup_604_hid0)

	mfspr	r11,SPRN_HID0

	ori	r11,r11,HID0_SIED|HID0_BHTE

	ori	r8,r11,HID0_BTCD
@@ -110,6 +113,7 @@ setup_604_hid0: 
	sync

	isync

	blr

SYM_FUNC_END(setup_604_hid0)



/* 7400 <= rev 2.7 and 7410 rev = 1.0 suffer from some

 * erratas we work around here.
@@ -125,13 +129,14 @@ setup_604_hid0: 
 * needed once we have applied workaround #5 (though it's

 * not set by Apple's firmware at least).

 */

setup_7400_workarounds:

SYM_FUNC_START_LOCAL(setup_7400_workarounds)

	mfpvr	r3

	rlwinm	r3,r3,0,20,31

	cmpwi	0,r3,0x0207

	ble	1f

	blr

setup_7410_workarounds:

SYM_FUNC_END(setup_7400_workarounds)

SYM_FUNC_START_LOCAL(setup_7410_workarounds)

	mfpvr	r3

	rlwinm	r3,r3,0,20,31

	cmpwi	0,r3,0x0100
@@ -151,6 +156,7 @@ setup_7410_workarounds: 
	sync

	isync

	blr

SYM_FUNC_END(setup_7410_workarounds)



/* 740/750/7400/7410

 * Enable Store Gathering (SGE), Address Broadcast (ABE),
@@ -158,7 +164,7 @@ setup_7410_workarounds: 
 * Dynamic Power Management (DPM), Speculative (SPD)

 * Clear Instruction cache throttling (ICTC)

 */

setup_750_7400_hid0:

SYM_FUNC_START_LOCAL(setup_750_7400_hid0)

	mfspr	r11,SPRN_HID0

	ori	r11,r11,HID0_SGE | HID0_ABE | HID0_BHTE | HID0_BTIC

	oris	r11,r11,HID0_DPM@h
@@ -177,12 +183,13 @@ END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM) 
	sync

	isync

	blr

SYM_FUNC_END(setup_750_7400_hid0)



/* 750cx specific

 * Looks like we have to disable NAP feature for some PLL settings...

 * (waiting for confirmation)

 */

setup_750cx:

SYM_FUNC_START_LOCAL(setup_750cx)

	mfspr	r10, SPRN_HID1

	rlwinm	r10,r10,4,28,31

	cmpwi	cr0,r10,7
@@ -196,11 +203,13 @@ setup_750cx: 
	andc	r6,r6,r7

	stw	r6,CPU_SPEC_FEATURES(r4)

	blr

SYM_FUNC_END(setup_750cx)



/* 750fx specific

 */

setup_750fx:

SYM_FUNC_START_LOCAL(setup_750fx)

	blr

SYM_FUNC_END(setup_750fx)



/* MPC 745x

 * Enable Store Gathering (SGE), Branch Folding (FOLD)
@@ -212,7 +221,7 @@ setup_750fx: 
 * Clear Instruction cache throttling (ICTC)

 * Enable L2 HW prefetch

 */

setup_745x_specifics:

SYM_FUNC_START_LOCAL(setup_745x_specifics)

	/* We check for the presence of an L3 cache setup by

	 * the firmware. If any, we disable NAP capability as

	 * it's known to be bogus on rev 2.1 and earlier
@@ -270,6 +279,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM) 
	sync

	isync

	blr

SYM_FUNC_END(setup_745x_specifics)



/*

 * Initialize the FPU registers. This is needed to work around an errata

arch/powerpc/kernel/cpu_setup_e500.S

+6 −2
Original line number Diff line number Diff line
@@ -8,6 +8,8 @@ 
 * Benjamin Herrenschmidt <benh@kernel.crashing.org>

 */



#include <linux/linkage.h>



#include <asm/page.h>

#include <asm/processor.h>

#include <asm/cputable.h>
@@ -274,7 +276,7 @@ _GLOBAL(flush_dcache_L1) 


	blr



has_L2_cache:

SYM_FUNC_START_LOCAL(has_L2_cache)

	/* skip L2 cache on P2040/P2040E as they have no L2 cache */

	mfspr	r3, SPRN_SVR

	/* shift right by 8 bits and clear E bit of SVR */
@@ -290,9 +292,10 @@ has_L2_cache: 
1:

	li	r3, 0

	blr

SYM_FUNC_END(has_L2_cache)



/* flush backside L2 cache */

flush_backside_L2_cache:

SYM_FUNC_START_LOCAL(flush_backside_L2_cache)

	mflr	r10

	bl	has_L2_cache

	mtlr	r10
@@ -313,6 +316,7 @@ flush_backside_L2_cache: 
	bne	1b

2:

	blr

SYM_FUNC_END(flush_backside_L2_cache)



_GLOBAL(cpu_down_flush_e500v2)

	mflr r0

arch/powerpc/kernel/entry_32.S

+6 −3
Original line number Diff line number Diff line
@@ -18,6 +18,8 @@ 
#include <linux/err.h>

#include <linux/sys.h>

#include <linux/threads.h>

#include <linux/linkage.h>



#include <asm/reg.h>

#include <asm/page.h>

#include <asm/mmu.h>
@@ -74,17 +76,18 @@ _ASM_NOKPROBE_SYMBOL(prepare_transfer_to_handler) 
#endif /* CONFIG_PPC_BOOK3S_32 || CONFIG_PPC_E500 */



#if defined(CONFIG_PPC_KUEP) && defined(CONFIG_PPC_BOOK3S_32)

	.globl	__kuep_lock

__kuep_lock:

SYM_FUNC_START(__kuep_lock)

	lwz	r9, THREAD+THSR0(r2)

	update_user_segments_by_4 r9, r10, r11, r12

	blr

SYM_FUNC_END(__kuep_lock)



__kuep_unlock:

SYM_FUNC_START_LOCAL(__kuep_unlock)

	lwz	r9, THREAD+THSR0(r2)

	rlwinm  r9,r9,0,~SR_NX

	update_user_segments_by_4 r9, r10, r11, r12

	blr

SYM_FUNC_END(__kuep_unlock)



.macro	kuep_lock

	bl	__kuep_lock

arch/powerpc/kernel/head_40x.S

+4 −1
Original line number Diff line number Diff line
@@ -28,6 +28,8 @@ 
#include <linux/init.h>

#include <linux/pgtable.h>

#include <linux/sizes.h>

#include <linux/linkage.h>



#include <asm/processor.h>

#include <asm/page.h>

#include <asm/mmu.h>
@@ -662,7 +664,7 @@ start_here: 
 * kernel initialization.  This maps the first 32 MBytes of memory 1:1

 * virtual to physical and more importantly sets the cache mode.

 */

initial_mmu:

SYM_FUNC_START_LOCAL(initial_mmu)

	tlbia			/* Invalidate all TLB entries */

	isync
@@ -711,6 +713,7 @@ initial_mmu: 
	mtspr	SPRN_EVPR,r0



	blr

SYM_FUNC_END(initial_mmu)



_GLOBAL(abort)

        mfspr   r13,SPRN_DBCR0

arch/powerpc/kernel/head_85xx.S

+4 −1
Original line number Diff line number Diff line
@@ -29,6 +29,8 @@ 
#include <linux/init.h>

#include <linux/threads.h>

#include <linux/pgtable.h>

#include <linux/linkage.h>



#include <asm/processor.h>

#include <asm/page.h>

#include <asm/mmu.h>
@@ -885,7 +887,7 @@ KernelSPE: 
 * Translate the effec addr in r3 to phys addr. The phys addr will be put

 * into r3(higher 32bit) and r4(lower 32bit)

 */

get_phys_addr:

SYM_FUNC_START_LOCAL(get_phys_addr)

	mfmsr	r8

	mfspr	r9,SPRN_PID

	rlwinm	r9,r9,16,0x3fff0000	/* turn PID into MAS6[SPID] */
@@ -907,6 +909,7 @@ get_phys_addr: 
	mfspr	r3,SPRN_MAS7

#endif

	blr

SYM_FUNC_END(get_phys_addr)



/*

 * Global functions