Commit 2d9da585 authored by Umesh Nerlige Ramappa's avatar Umesh Nerlige Ramappa Committed by John Harrison
Browse files

drm/i915/perf: Fix noa wait predication for DG2 



Predication for batch buffer commands changed in XEHPSDV.
MI_BATCH_BUFFER_START predicates based on MI_SET_PREDICATE_RESULT
register. The MI_SET_PREDICATE_RESULT register can only be modified
with MI_SET_PREDICATE command. When configured, the MI_SET_PREDICATE
command sets MI_SET_PREDICATE_RESULT based on bit 0 of
MI_PREDICATE_RESULT_2. Use this to configure predication in noa_wait.

Signed-off-by: default avatarUmesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: default avatarAshutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: default avatarJohn Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221026222102.5526-4-umesh.nerlige.ramappa@intel.com
parent 81d5f7d9

drivers/gpu/drm/i915/gt/intel_engine_regs.h

+1 −0
Original line number Diff line number Diff line
@@ -201,6 +201,7 @@ 
#define RING_CONTEXT_STATUS_PTR(base)		_MMIO((base) + 0x3a0)

#define RING_CTX_TIMESTAMP(base)		_MMIO((base) + 0x3a8) /* gen8+ */

#define RING_PREDICATE_RESULT(base)		_MMIO((base) + 0x3b8)

#define MI_PREDICATE_RESULT_2_ENGINE(base)	_MMIO((base) + 0x3bc)

#define RING_FORCE_TO_NONPRIV(base, i)		_MMIO(((base) + 0x4D0) + (i) * 4)

#define   RING_FORCE_TO_NONPRIV_DENY		REG_BIT(30)

#define   RING_FORCE_TO_NONPRIV_ADDRESS_MASK	REG_GENMASK(25, 2)

drivers/gpu/drm/i915/i915_perf.c

+20 −4
Original line number Diff line number Diff line
@@ -286,6 +286,7 @@ static u32 i915_perf_stream_paranoid = true; 
#define OAREPORT_REASON_CTX_SWITCH     (1<<3)

#define OAREPORT_REASON_CLK_RATIO      (1<<5)



#define HAS_MI_SET_PREDICATE(i915) (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))



/* For sysctl proc_dointvec_minmax of i915_oa_max_sample_rate

 *
@@ -1760,6 +1761,9 @@ static int alloc_noa_wait(struct i915_perf_stream *stream) 
		DELTA_TARGET,

		N_CS_GPR

	};

	i915_reg_t mi_predicate_result = HAS_MI_SET_PREDICATE(i915) ?

					  MI_PREDICATE_RESULT_2_ENGINE(base) :

					  MI_PREDICATE_RESULT_1(RENDER_RING_BASE);



	bo = i915_gem_object_create_internal(i915, 4096);

	if (IS_ERR(bo)) {
@@ -1797,7 +1801,7 @@ static int alloc_noa_wait(struct i915_perf_stream *stream) 
			stream, cs, true /* save */, CS_GPR(i),

			INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);

	cs = save_restore_register(

		stream, cs, true /* save */, MI_PREDICATE_RESULT_1(RENDER_RING_BASE),

		stream, cs, true /* save */, mi_predicate_result,

		INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1);



	/* First timestamp snapshot location. */
@@ -1851,7 +1855,10 @@ static int alloc_noa_wait(struct i915_perf_stream *stream) 
	 */

	*cs++ = MI_LOAD_REGISTER_REG | (3 - 2);

	*cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE));

	*cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1(RENDER_RING_BASE));

	*cs++ = i915_mmio_reg_offset(mi_predicate_result);



	if (HAS_MI_SET_PREDICATE(i915))

		*cs++ = MI_SET_PREDICATE | 1;



	/* Restart from the beginning if we had timestamps roll over. */

	*cs++ = (GRAPHICS_VER(i915) < 8 ?
@@ -1861,6 +1868,9 @@ static int alloc_noa_wait(struct i915_perf_stream *stream) 
	*cs++ = i915_ggtt_offset(vma) + (ts0 - batch) * 4;

	*cs++ = 0;



	if (HAS_MI_SET_PREDICATE(i915))

		*cs++ = MI_SET_PREDICATE;



	/*

	 * Now add the diff between to previous timestamps and add it to :

	 *      (((1 * << 64) - 1) - delay_ns)
@@ -1888,7 +1898,10 @@ static int alloc_noa_wait(struct i915_perf_stream *stream) 
	 */

	*cs++ = MI_LOAD_REGISTER_REG | (3 - 2);

	*cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE));

	*cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1(RENDER_RING_BASE));

	*cs++ = i915_mmio_reg_offset(mi_predicate_result);



	if (HAS_MI_SET_PREDICATE(i915))

		*cs++ = MI_SET_PREDICATE | 1;



	/* Predicate the jump.  */

	*cs++ = (GRAPHICS_VER(i915) < 8 ?
@@ -1898,13 +1911,16 @@ static int alloc_noa_wait(struct i915_perf_stream *stream) 
	*cs++ = i915_ggtt_offset(vma) + (jump - batch) * 4;

	*cs++ = 0;



	if (HAS_MI_SET_PREDICATE(i915))

		*cs++ = MI_SET_PREDICATE;



	/* Restore registers. */

	for (i = 0; i < N_CS_GPR; i++)

		cs = save_restore_register(

			stream, cs, false /* restore */, CS_GPR(i),

			INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);

	cs = save_restore_register(

		stream, cs, false /* restore */, MI_PREDICATE_RESULT_1(RENDER_RING_BASE),

		stream, cs, false /* restore */, mi_predicate_result,

		INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1);



	/* And return to the ring. */