Commit 2d987e64 authored by Mark Brown's avatar Mark Brown Committed by Catalin Marinas
Browse files

arm64/sysreg: Add _EL1 into ID_AA64MMFR0_EL1 definition names 



Normally we include the full register name in the defines for fields within
registers but this has not been followed for ID registers. In preparation
for automatic generation of defines add the _EL1s into the defines for
ID_AA64MMFR0_EL1 to follow the convention. No functional changes.

Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Reviewed-by: default avatarKristina Martsenko <kristina.martsenko@arm.com>
Link: https://lore.kernel.org/r/20220905225425.1871461-5-broonie@kernel.org


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent d9b230f6

arch/arm64/include/asm/assembler.h

+2 −2
Original line number Original line Diff line number Diff line
@@ -384,8 +384,8 @@ alternative_cb_end 
	.macro	tcr_compute_pa_size, tcr, pos, tmp0, tmp1

	.macro	tcr_compute_pa_size, tcr, pos, tmp0, tmp1

	mrs	\tmp0, ID_AA64MMFR0_EL1

	mrs	\tmp0, ID_AA64MMFR0_EL1

	// Narrow PARange to fit the PS field in TCR_ELx

	// Narrow PARange to fit the PS field in TCR_ELx

	ubfx	\tmp0, \tmp0, #ID_AA64MMFR0_PARANGE_SHIFT, #3

	ubfx	\tmp0, \tmp0, #ID_AA64MMFR0_EL1_PARANGE_SHIFT, #3

	mov	\tmp1, #ID_AA64MMFR0_PARANGE_MAX

	mov	\tmp1, #ID_AA64MMFR0_EL1_PARANGE_MAX

	cmp	\tmp0, \tmp1

	cmp	\tmp0, \tmp1

	csel	\tmp0, \tmp1, \tmp0, hi

	csel	\tmp0, \tmp1, \tmp0, hi

	bfi	\tcr, \tmp0, \pos, #3

	bfi	\tcr, \tmp0, \pos, #3

arch/arm64/include/asm/cpufeature.h

+19 −19
Original line number Original line Diff line number Diff line
@@ -597,8 +597,8 @@ static inline s64 arm64_ftr_value(const struct arm64_ftr_bits *ftrp, u64 val) 




static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0)

static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0)

{

{

	return cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_BIGENDEL_SHIFT) == 0x1 ||

	return cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_EL1_BIGENDEL_SHIFT) == 0x1 ||

		cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_BIGENDEL0_SHIFT) == 0x1;

		cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT) == 0x1;

}

}





static inline bool id_aa64pfr0_32bit_el1(u64 pfr0)

static inline bool id_aa64pfr0_32bit_el1(u64 pfr0)
@@ -694,10 +694,10 @@ static inline bool system_supports_4kb_granule(void) 




	mmfr0 =	read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);

	mmfr0 =	read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);

	val = cpuid_feature_extract_unsigned_field(mmfr0,

	val = cpuid_feature_extract_unsigned_field(mmfr0,

						ID_AA64MMFR0_TGRAN4_SHIFT);

						ID_AA64MMFR0_EL1_TGRAN4_SHIFT);





	return (val >= ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN) &&

	return (val >= ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN) &&

	       (val <= ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX);

	       (val <= ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX);

}

}





static inline bool system_supports_64kb_granule(void)

static inline bool system_supports_64kb_granule(void)
@@ -707,10 +707,10 @@ static inline bool system_supports_64kb_granule(void) 




	mmfr0 =	read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);

	mmfr0 =	read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);

	val = cpuid_feature_extract_unsigned_field(mmfr0,

	val = cpuid_feature_extract_unsigned_field(mmfr0,

						ID_AA64MMFR0_TGRAN64_SHIFT);

						ID_AA64MMFR0_EL1_TGRAN64_SHIFT);





	return (val >= ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN) &&

	return (val >= ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN) &&

	       (val <= ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX);

	       (val <= ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX);

}

}





static inline bool system_supports_16kb_granule(void)

static inline bool system_supports_16kb_granule(void)
@@ -720,10 +720,10 @@ static inline bool system_supports_16kb_granule(void) 




	mmfr0 =	read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);

	mmfr0 =	read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);

	val = cpuid_feature_extract_unsigned_field(mmfr0,

	val = cpuid_feature_extract_unsigned_field(mmfr0,

						ID_AA64MMFR0_TGRAN16_SHIFT);

						ID_AA64MMFR0_EL1_TGRAN16_SHIFT);





	return (val >= ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN) &&

	return (val >= ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN) &&

	       (val <= ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX);

	       (val <= ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX);

}

}





static inline bool system_supports_mixed_endian_el0(void)

static inline bool system_supports_mixed_endian_el0(void)
@@ -738,7 +738,7 @@ static inline bool system_supports_mixed_endian(void) 




	mmfr0 =	read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);

	mmfr0 =	read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);

	val = cpuid_feature_extract_unsigned_field(mmfr0,

	val = cpuid_feature_extract_unsigned_field(mmfr0,

						ID_AA64MMFR0_BIGENDEL_SHIFT);

						ID_AA64MMFR0_EL1_BIGENDEL_SHIFT);





	return val == 0x1;

	return val == 0x1;

}

}
@@ -840,13 +840,13 @@ extern int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt); 
static inline u32 id_aa64mmfr0_parange_to_phys_shift(int parange)

static inline u32 id_aa64mmfr0_parange_to_phys_shift(int parange)

{

{

	switch (parange) {

	switch (parange) {

	case ID_AA64MMFR0_PARANGE_32: return 32;

	case ID_AA64MMFR0_EL1_PARANGE_32: return 32;

	case ID_AA64MMFR0_PARANGE_36: return 36;

	case ID_AA64MMFR0_EL1_PARANGE_36: return 36;

	case ID_AA64MMFR0_PARANGE_40: return 40;

	case ID_AA64MMFR0_EL1_PARANGE_40: return 40;

	case ID_AA64MMFR0_PARANGE_42: return 42;

	case ID_AA64MMFR0_EL1_PARANGE_42: return 42;

	case ID_AA64MMFR0_PARANGE_44: return 44;

	case ID_AA64MMFR0_EL1_PARANGE_44: return 44;

	case ID_AA64MMFR0_PARANGE_48: return 48;

	case ID_AA64MMFR0_EL1_PARANGE_48: return 48;

	case ID_AA64MMFR0_PARANGE_52: return 52;

	case ID_AA64MMFR0_EL1_PARANGE_52: return 52;

	/*

	/*

	 * A future PE could use a value unknown to the kernel.

	 * A future PE could use a value unknown to the kernel.

	 * However, by the "D10.1.4 Principles of the ID scheme

	 * However, by the "D10.1.4 Principles of the ID scheme

arch/arm64/include/asm/el2_setup.h

+1 −1
Original line number Original line Diff line number Diff line
@@ -132,7 +132,7 @@ 
/* Disable any fine grained traps */

/* Disable any fine grained traps */

.macro __init_el2_fgt

.macro __init_el2_fgt

	mrs	x1, id_aa64mmfr0_el1

	mrs	x1, id_aa64mmfr0_el1

	ubfx	x1, x1, #ID_AA64MMFR0_FGT_SHIFT, #4

	ubfx	x1, x1, #ID_AA64MMFR0_EL1_FGT_SHIFT, #4

	cbz	x1, .Lskip_fgt_\@

	cbz	x1, .Lskip_fgt_\@





	mov	x0, xzr

	mov	x0, xzr

arch/arm64/include/asm/kvm_pgtable.h

+3 −3
Original line number Original line Diff line number Diff line
@@ -16,9 +16,9 @@ 
static inline u64 kvm_get_parange(u64 mmfr0)

static inline u64 kvm_get_parange(u64 mmfr0)

{

{

	u64 parange = cpuid_feature_extract_unsigned_field(mmfr0,

	u64 parange = cpuid_feature_extract_unsigned_field(mmfr0,

				ID_AA64MMFR0_PARANGE_SHIFT);

				ID_AA64MMFR0_EL1_PARANGE_SHIFT);

	if (parange > ID_AA64MMFR0_PARANGE_MAX)

	if (parange > ID_AA64MMFR0_EL1_PARANGE_MAX)

		parange = ID_AA64MMFR0_PARANGE_MAX;

		parange = ID_AA64MMFR0_EL1_PARANGE_MAX;





	return parange;

	return parange;

}

}

arch/arm64/include/asm/sysreg.h

+53 −53
Original line number Original line Diff line number Diff line
@@ -733,53 +733,53 @@ 
#define ID_AA64PFR1_MTE_ASYMM		0x3

#define ID_AA64PFR1_MTE_ASYMM		0x3





/* id_aa64mmfr0 */

/* id_aa64mmfr0 */

#define ID_AA64MMFR0_ECV_SHIFT		60

#define ID_AA64MMFR0_EL1_ECV_SHIFT		60

#define ID_AA64MMFR0_FGT_SHIFT		56

#define ID_AA64MMFR0_EL1_FGT_SHIFT		56

#define ID_AA64MMFR0_EXS_SHIFT		44

#define ID_AA64MMFR0_EL1_EXS_SHIFT		44

#define ID_AA64MMFR0_TGRAN4_2_SHIFT	40

#define ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT		40

#define ID_AA64MMFR0_TGRAN64_2_SHIFT	36

#define ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT	36

#define ID_AA64MMFR0_TGRAN16_2_SHIFT	32

#define ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT	32

#define ID_AA64MMFR0_TGRAN4_SHIFT	28

#define ID_AA64MMFR0_EL1_TGRAN4_SHIFT		28

#define ID_AA64MMFR0_TGRAN64_SHIFT	24

#define ID_AA64MMFR0_EL1_TGRAN64_SHIFT		24

#define ID_AA64MMFR0_TGRAN16_SHIFT	20

#define ID_AA64MMFR0_EL1_TGRAN16_SHIFT		20

#define ID_AA64MMFR0_BIGENDEL0_SHIFT	16

#define ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT	16

#define ID_AA64MMFR0_SNSMEM_SHIFT	12

#define ID_AA64MMFR0_EL1_SNSMEM_SHIFT		12

#define ID_AA64MMFR0_BIGENDEL_SHIFT	8

#define ID_AA64MMFR0_EL1_BIGENDEL_SHIFT		8

#define ID_AA64MMFR0_ASID_SHIFT		4

#define ID_AA64MMFR0_EL1_ASID_SHIFT		4

#define ID_AA64MMFR0_PARANGE_SHIFT	0

#define ID_AA64MMFR0_EL1_PARANGE_SHIFT		0





#define ID_AA64MMFR0_ASID_8		0x0

#define ID_AA64MMFR0_EL1_ASID_8			0x0

#define ID_AA64MMFR0_ASID_16		0x2

#define ID_AA64MMFR0_EL1_ASID_16		0x2





#define ID_AA64MMFR0_TGRAN4_NI			0xf

#define ID_AA64MMFR0_EL1_TGRAN4_NI		0xf

#define ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN	0x0

#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN	0x0

#define ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX	0x7

#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX	0x7

#define ID_AA64MMFR0_TGRAN64_NI			0xf

#define ID_AA64MMFR0_EL1_TGRAN64_NI		0xf

#define ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN	0x0

#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN	0x0

#define ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX	0x7

#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX	0x7

#define ID_AA64MMFR0_TGRAN16_NI			0x0

#define ID_AA64MMFR0_EL1_TGRAN16_NI		0x0

#define ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN	0x1

#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN	0x1

#define ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX	0xf

#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX	0xf





#define ID_AA64MMFR0_PARANGE_32		0x0

#define ID_AA64MMFR0_EL1_PARANGE_32		0x0

#define ID_AA64MMFR0_PARANGE_36		0x1

#define ID_AA64MMFR0_EL1_PARANGE_36		0x1

#define ID_AA64MMFR0_PARANGE_40		0x2

#define ID_AA64MMFR0_EL1_PARANGE_40		0x2

#define ID_AA64MMFR0_PARANGE_42		0x3

#define ID_AA64MMFR0_EL1_PARANGE_42		0x3

#define ID_AA64MMFR0_PARANGE_44		0x4

#define ID_AA64MMFR0_EL1_PARANGE_44		0x4

#define ID_AA64MMFR0_PARANGE_48		0x5

#define ID_AA64MMFR0_EL1_PARANGE_48		0x5

#define ID_AA64MMFR0_PARANGE_52		0x6

#define ID_AA64MMFR0_EL1_PARANGE_52		0x6





#define ARM64_MIN_PARANGE_BITS		32

#define ARM64_MIN_PARANGE_BITS		32





#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_DEFAULT	0x0

#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_DEFAULT	0x0

#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_NONE	0x1

#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_NONE		0x1

#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MIN	0x2

#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MIN		0x2

#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MAX	0x7

#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MAX		0x7





#ifdef CONFIG_ARM64_PA_BITS_52

#ifdef CONFIG_ARM64_PA_BITS_52

#define ID_AA64MMFR0_PARANGE_MAX	ID_AA64MMFR0_PARANGE_52

#define ID_AA64MMFR0_EL1_PARANGE_MAX	ID_AA64MMFR0_EL1_PARANGE_52

#else

#else

#define ID_AA64MMFR0_PARANGE_MAX	ID_AA64MMFR0_PARANGE_48

#define ID_AA64MMFR0_EL1_PARANGE_MAX	ID_AA64MMFR0_EL1_PARANGE_48

#endif

#endif





/* id_aa64mmfr1 */

/* id_aa64mmfr1 */
@@ -951,20 +951,20 @@ 
#define ID_PFR1_PROGMOD_SHIFT		0

#define ID_PFR1_PROGMOD_SHIFT		0





#if defined(CONFIG_ARM64_4K_PAGES)

#if defined(CONFIG_ARM64_4K_PAGES)

#define ID_AA64MMFR0_TGRAN_SHIFT		ID_AA64MMFR0_TGRAN4_SHIFT

#define ID_AA64MMFR0_EL1_TGRAN_SHIFT		ID_AA64MMFR0_EL1_TGRAN4_SHIFT

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN

#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX

#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX

#define ID_AA64MMFR0_TGRAN_2_SHIFT		ID_AA64MMFR0_TGRAN4_2_SHIFT

#define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT		ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT

#elif defined(CONFIG_ARM64_16K_PAGES)

#elif defined(CONFIG_ARM64_16K_PAGES)

#define ID_AA64MMFR0_TGRAN_SHIFT		ID_AA64MMFR0_TGRAN16_SHIFT

#define ID_AA64MMFR0_EL1_TGRAN_SHIFT		ID_AA64MMFR0_EL1_TGRAN16_SHIFT

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN

#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX

#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX

#define ID_AA64MMFR0_TGRAN_2_SHIFT		ID_AA64MMFR0_TGRAN16_2_SHIFT

#define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT		ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT

#elif defined(CONFIG_ARM64_64K_PAGES)

#elif defined(CONFIG_ARM64_64K_PAGES)

#define ID_AA64MMFR0_TGRAN_SHIFT		ID_AA64MMFR0_TGRAN64_SHIFT

#define ID_AA64MMFR0_EL1_TGRAN_SHIFT		ID_AA64MMFR0_EL1_TGRAN64_SHIFT

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN

#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX

#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX

#define ID_AA64MMFR0_TGRAN_2_SHIFT		ID_AA64MMFR0_TGRAN64_2_SHIFT

#define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT		ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT

#endif

#endif





#define MVFR2_FPMISC_SHIFT		4

#define MVFR2_FPMISC_SHIFT		4