Commit 2d701243 authored by Fuad Tabba's avatar Fuad Tabba Committed by Marc Zyngier
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KVM: arm64: Add config register bit definitions 



Add hardware configuration register bit definitions for HCR_EL2
and MDCR_EL2. Future patches toggle these hyp configuration
register bits to trap on certain accesses.

No functional change intended.

Acked-by: default avatarWill Deacon <will@kernel.org>
Signed-off-by: default avatarFuad Tabba <tabba@google.com>
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210817081134.2918285-11-tabba@google.com
parent 95b54c3e

arch/arm64/include/asm/kvm_arm.h

+22 −0
Original line number Diff line number Diff line
@@ -12,8 +12,13 @@ 
#include <asm/types.h>



/* Hyp Configuration Register (HCR) bits */



#define HCR_TID5	(UL(1) << 58)

#define HCR_DCT		(UL(1) << 57)

#define HCR_ATA_SHIFT	56

#define HCR_ATA		(UL(1) << HCR_ATA_SHIFT)

#define HCR_AMVOFFEN	(UL(1) << 51)

#define HCR_FIEN	(UL(1) << 47)

#define HCR_FWB		(UL(1) << 46)

#define HCR_API		(UL(1) << 41)

#define HCR_APK		(UL(1) << 40)
@@ -56,6 +61,7 @@ 
#define HCR_PTW		(UL(1) << 2)

#define HCR_SWIO	(UL(1) << 1)

#define HCR_VM		(UL(1) << 0)

#define HCR_RES0	((UL(1) << 48) | (UL(1) << 39))



/*

 * The bits we set in HCR:
@@ -277,11 +283,21 @@ 
#define CPTR_EL2_TZ	(1 << 8)

#define CPTR_NVHE_EL2_RES1	0x000032ff /* known RES1 bits in CPTR_EL2 (nVHE) */

#define CPTR_EL2_DEFAULT	CPTR_NVHE_EL2_RES1

#define CPTR_NVHE_EL2_RES0	(GENMASK(63, 32) |	\

				 GENMASK(29, 21) |	\

				 GENMASK(19, 14) |	\

				 BIT(11))



/* Hyp Debug Configuration Register bits */

#define MDCR_EL2_E2TB_MASK	(UL(0x3))

#define MDCR_EL2_E2TB_SHIFT	(UL(24))

#define MDCR_EL2_HPMFZS		(UL(1) << 36)

#define MDCR_EL2_HPMFZO		(UL(1) << 29)

#define MDCR_EL2_MTPME		(UL(1) << 28)

#define MDCR_EL2_TDCC		(UL(1) << 27)

#define MDCR_EL2_HCCD		(UL(1) << 23)

#define MDCR_EL2_TTRF		(UL(1) << 19)

#define MDCR_EL2_HPMD		(UL(1) << 17)

#define MDCR_EL2_TPMS		(UL(1) << 14)

#define MDCR_EL2_E2PB_MASK	(UL(0x3))

#define MDCR_EL2_E2PB_SHIFT	(UL(12))
@@ -293,6 +309,12 @@ 
#define MDCR_EL2_TPM		(UL(1) << 6)

#define MDCR_EL2_TPMCR		(UL(1) << 5)

#define MDCR_EL2_HPMN_MASK	(UL(0x1F))

#define MDCR_EL2_RES0		(GENMASK(63, 37) |	\

				 GENMASK(35, 30) |	\

				 GENMASK(25, 24) |	\

				 GENMASK(22, 20) |	\

				 BIT(18) |		\

				 GENMASK(16, 15))



/* For compatibility with fault code shared with 32-bit */

#define FSC_FAULT	ESR_ELx_FSC_FAULT