Commit 2d5c0415 authored by Praful Swarnakar's avatar Praful Swarnakar Committed by Alex Deucher
Browse files

drm/amdgpu: Fix style issues in amdgpu_psp.c 



Fixes the following to align to linux coding style:

WARNING: Block comments use a trailing */ on a separate line
WARNING: Block comments should align the * on each line

Cc: Christian König <christian.koenig@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: default avatarPraful Swarnakar <Praful.Swarnakar@amd.com>
Reviewed-by: default avatarGuchun Chen <guchun.chen@amd.com>
Reviewed-by: default avatarSrinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ad19c200

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

+16 −12
Original line number Diff line number Diff line
@@ -438,14 +438,15 @@ static int psp_sw_init(void *handle) 
			/* If psp runtime database exists, then

			 * only enable two stage memory training

			 * when TWO_STAGE_DRAM_TRAINING bit is set

			 * in runtime database */

			 * in runtime database

			 */

			mem_training_ctx->enable_mem_training = true;

		}



	} else {

		/* If psp runtime database doesn't exist or

		 * is invalid, force enable two stage memory

		 * training */

		/* If psp runtime database doesn't exist or is

		 * invalid, force enable two stage memory training

		 */

		mem_training_ctx->enable_mem_training = true;

	}
@@ -797,7 +798,8 @@ static int psp_tmr_init(struct psp_context *psp) 
	tmr_size = PSP_TMR_SIZE(psp->adev);



	/* For ASICs support RLC autoload, psp will parse the toc

	 * and calculate the total size of TMR needed */

	 * and calculate the total size of TMR needed

	 */

	if (!amdgpu_sriov_vf(psp->adev) &&

	    psp->toc.start_addr &&

	    psp->toc.size_bytes &&
@@ -1728,7 +1730,8 @@ int psp_ras_trigger_error(struct psp_context *psp, 
		return -EINVAL;



	/* If err_event_athub occurs error inject was successful, however

	   return status from TA is no long reliable */

	 *  return status from TA is no long reliable

	 */

	if (amdgpu_ras_intr_triggered())

		return 0;
@@ -2577,7 +2580,8 @@ static int psp_load_non_psp_fw(struct psp_context *psp) 
		     ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||

		     ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))

			/* PSP only receive one SDMA fw for sienna_cichlid,

			 * as all four sdma fw are same */

			 * as all four sdma fw are same

			 */

			continue;



		psp_print_fw_hdr(psp, ucode);