Commit 2d53b579 authored by Candice Li's avatar Candice Li Committed by Alex Deucher
Browse files

drm/amdgpu: Add convert_error_address function for umc v8_10 



Add convert_error_address for umc v8_10.

Signed-off-by: default avatarCandice Li <candice.li@amd.com>
Reviewed-by: default avatarTao Zhou <tao.zhou1@amd.com>
Reviewed-by: default avatarStanley.Yang <Stanley.Yang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 22106ed0

drivers/gpu/drm/amd/amdgpu/umc_v8_10.c

+42 −31
Original line number Diff line number Diff line
@@ -209,48 +209,22 @@ static int umc_v8_10_swizzle_mode_na_to_pa(struct amdgpu_device *adev, 
	return 0;

}



static void umc_v8_10_query_error_address(struct amdgpu_device *adev,

					 struct ras_err_data *err_data,

					 uint32_t umc_reg_offset,

					 uint32_t node_inst,

					 uint32_t ch_inst,

					 uint32_t umc_inst)

void umc_v8_10_convert_error_address(struct amdgpu_device *adev,

				    struct ras_err_data *err_data, uint64_t err_addr,

				    uint32_t ch_inst, uint32_t umc_inst,

				    uint32_t node_inst, uint64_t mc_umc_status)

{

	uint64_t mc_umc_status_addr;

	uint64_t mc_umc_status, err_addr;

	uint64_t mc_umc_addrt0, na_err_addr_base;

	uint64_t na_err_addr_base;

	uint64_t na_err_addr, retired_page_addr;

	uint32_t channel_index, addr_lsb, col = 0;

	int ret = 0;



	mc_umc_status_addr =

		SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0);

	mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4);



	if (mc_umc_status == 0)

		return;



	if (!err_data->err_addr) {

		/* clear umc status */

		WREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL);

		return;

	}



	channel_index =

		adev->umc.channel_idx_tbl[node_inst * adev->umc.umc_inst_num *

					adev->umc.channel_inst_num +

					umc_inst * adev->umc.channel_inst_num +

					ch_inst];



	/* calculate error address if ue error is detected */

	if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&

	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, AddrV) == 1 &&

	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1) {



		mc_umc_addrt0 = SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0);

		err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4);

		err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);



	/* the lowest lsb bits should be ignored */

	addr_lsb = REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, AddrLsb);

	err_addr &= ~((0x1ULL << addr_lsb) - 1);
@@ -274,6 +248,43 @@ static void umc_v8_10_query_error_address(struct amdgpu_device *adev, 
	}

}



static void umc_v8_10_query_error_address(struct amdgpu_device *adev,

					 struct ras_err_data *err_data,

					 uint32_t umc_reg_offset,

					 uint32_t node_inst,

					 uint32_t ch_inst,

					 uint32_t umc_inst)

{

	uint64_t mc_umc_status_addr;

	uint64_t mc_umc_status, err_addr;

	uint64_t mc_umc_addrt0;



	mc_umc_status_addr =

		SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0);

	mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4);



	if (mc_umc_status == 0)

		return;



	if (!err_data->err_addr) {

		/* clear umc status */

		WREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL);

		return;

	}



	/* calculate error address if ue error is detected */

	if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&

	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, AddrV) == 1 &&

	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1) {



		mc_umc_addrt0 = SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0);

		err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4);

		err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);



		umc_v8_10_convert_error_address(adev, err_data, err_addr,

					ch_inst, umc_inst, node_inst, mc_umc_status);

	}



	/* clear umc status */

	WREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL);

}