Commit 2cdee50e authored by Colin Ian King's avatar Colin Ian King Committed by Stephen Boyd
Browse files

clk: lmk04832: Fix spelling mistakes in dev_err messages and comments 



There are handful of spelling mistakes in two dev_err error messages
and comments. Fix them.

Signed-off-by: default avatarColin Ian King <colin.king@canonical.com>
Link: https://lore.kernel.org/r/20210629102956.17901-1-colin.king@canonical.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent b424f73b

drivers/clk/clk-lmk04832.c

+4 −4
Original line number Original line Diff line number Diff line
@@ -519,7 +519,7 @@ static long lmk04832_vco_round_rate(struct clk_hw *hw, unsigned long rate, 




	vco_rate = lmk04832_calc_pll2_params(*prate, rate, &n, &p, &r);

	vco_rate = lmk04832_calc_pll2_params(*prate, rate, &n, &p, &r);

	if (vco_rate < 0) {

	if (vco_rate < 0) {

		dev_err(lmk->dev, "PLL2 parmeters out of range\n");

		dev_err(lmk->dev, "PLL2 parameters out of range\n");

		return vco_rate;

		return vco_rate;

	}

	}
@@ -550,7 +550,7 @@ static int lmk04832_vco_set_rate(struct clk_hw *hw, unsigned long rate, 




	vco_rate = lmk04832_calc_pll2_params(prate, rate, &n, &p, &r);

	vco_rate = lmk04832_calc_pll2_params(prate, rate, &n, &p, &r);

	if (vco_rate < 0) {

	if (vco_rate < 0) {

		dev_err(lmk->dev, "failed to determine PLL2 parmeters\n");

		dev_err(lmk->dev, "failed to determine PLL2 parameters\n");

		return vco_rate;

		return vco_rate;

	}

	}
@@ -573,7 +573,7 @@ static int lmk04832_vco_set_rate(struct clk_hw *hw, unsigned long rate, 




	/*

	/*

	 * PLL2_N registers must be programmed after other PLL2 dividers are

	 * PLL2_N registers must be programmed after other PLL2 dividers are

	 * programed to ensure proper VCO frequency calibration

	 * programmed to ensure proper VCO frequency calibration

	 */

	 */

	ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_0,

	ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_0,

			   FIELD_GET(0x030000, n));

			   FIELD_GET(0x030000, n));
@@ -1120,7 +1120,7 @@ static int lmk04832_dclk_set_rate(struct clk_hw *hw, unsigned long rate, 
		return -EINVAL;

		return -EINVAL;

	}

	}





	/* Enable Duty Cycle Corretion */

	/* Enable Duty Cycle Correction */

	if (dclk_div == 1) {

	if (dclk_div == 1) {

		ret = regmap_update_bits(lmk->regmap,

		ret = regmap_update_bits(lmk->regmap,

					 LMK04832_REG_CLKOUT_CTRL3(dclk->id),

					 LMK04832_REG_CLKOUT_CTRL3(dclk->id),