Commit 2cbc876d authored by Michał Winiarski's avatar Michał Winiarski Committed by Matt Roper
Browse files

drm/i915: Use to_gt() helper 



Use to_gt() helper consistently throughout the codebase.
Pure mechanical s/i915->gt/to_gt(i915). No functional changes.

Signed-off-by: default avatarMichał Winiarski <michal.winiarski@intel.com>
Signed-off-by: default avatarAndi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211214193346.21231-10-andi.shyti@linux.intel.com
parent c68c74f5

drivers/gpu/drm/i915/i915_debugfs.c

+19 −19
Original line number Diff line number Diff line
@@ -66,7 +66,7 @@ static int i915_capabilities(struct seq_file *m, void *data) 
	intel_device_info_print_static(INTEL_INFO(i915), &p);

	intel_device_info_print_runtime(RUNTIME_INFO(i915), &p);

	i915_print_iommu_status(i915, &p);

	intel_gt_info_print(&i915->gt.info, &p);

	intel_gt_info_print(&to_gt(i915)->info, &p);

	intel_driver_caps_print(&i915->caps, &p);



	kernel_param_lock(THIS_MODULE);
@@ -294,7 +294,7 @@ static int i915_gpu_info_open(struct inode *inode, struct file *file) 


	gpu = NULL;

	with_intel_runtime_pm(&i915->runtime_pm, wakeref)

		gpu = i915_gpu_coredump(&i915->gt, ALL_ENGINES);

		gpu = i915_gpu_coredump(to_gt(i915), ALL_ENGINES);

	if (IS_ERR(gpu))

		return PTR_ERR(gpu);
@@ -352,7 +352,7 @@ static const struct file_operations i915_error_state_fops = { 
static int i915_frequency_info(struct seq_file *m, void *unused)

{

	struct drm_i915_private *i915 = node_to_i915(m->private);

	struct intel_gt *gt = &i915->gt;

	struct intel_gt *gt = to_gt(i915);

	struct drm_printer p = drm_seq_file_printer(m);



	intel_gt_pm_frequency_dump(gt, &p);
@@ -440,11 +440,11 @@ static int i915_swizzle_info(struct seq_file *m, void *data) 
static int i915_rps_boost_info(struct seq_file *m, void *data)

{

	struct drm_i915_private *dev_priv = node_to_i915(m->private);

	struct intel_rps *rps = &dev_priv->gt.rps;

	struct intel_rps *rps = &to_gt(dev_priv)->rps;



	seq_printf(m, "RPS enabled? %s\n", yesno(intel_rps_is_enabled(rps)));

	seq_printf(m, "RPS active? %s\n", yesno(intel_rps_is_active(rps)));

	seq_printf(m, "GPU busy? %s\n", yesno(dev_priv->gt.awake));

	seq_printf(m, "GPU busy? %s\n", yesno(to_gt(dev_priv)->awake));

	seq_printf(m, "Boosts outstanding? %d\n",

		   atomic_read(&rps->num_waiters));

	seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive));
@@ -477,7 +477,7 @@ static int i915_runtime_pm_status(struct seq_file *m, void *unused) 
	seq_printf(m, "Runtime power status: %s\n",

		   enableddisabled(!dev_priv->power_domains.init_wakeref));



	seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));

	seq_printf(m, "GPU idle: %s\n", yesno(!to_gt(dev_priv)->awake));

	seq_printf(m, "IRQs disabled: %s\n",

		   yesno(!intel_irqs_enabled(dev_priv)));

#ifdef CONFIG_PM
@@ -509,18 +509,18 @@ static int i915_engine_info(struct seq_file *m, void *unused) 
	wakeref = intel_runtime_pm_get(&i915->runtime_pm);



	seq_printf(m, "GT awake? %s [%d], %llums\n",

		   yesno(i915->gt.awake),

		   atomic_read(&i915->gt.wakeref.count),

		   ktime_to_ms(intel_gt_get_awake_time(&i915->gt)));

		   yesno(to_gt(i915)->awake),

		   atomic_read(&to_gt(i915)->wakeref.count),

		   ktime_to_ms(intel_gt_get_awake_time(to_gt(i915))));

	seq_printf(m, "CS timestamp frequency: %u Hz, %d ns\n",

		   i915->gt.clock_frequency,

		   i915->gt.clock_period_ns);

		   to_gt(i915)->clock_frequency,

		   to_gt(i915)->clock_period_ns);



	p = drm_seq_file_printer(m);

	for_each_uabi_engine(engine, i915)

		intel_engine_dump(engine, &p, "%s\n", engine->name);



	intel_gt_show_timelines(&i915->gt, &p, i915_request_show_with_schedule);

	intel_gt_show_timelines(to_gt(i915), &p, i915_request_show_with_schedule);



	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
@@ -559,14 +559,14 @@ static int i915_wedged_get(void *data, u64 *val) 
{

	struct drm_i915_private *i915 = data;



	return intel_gt_debugfs_reset_show(&i915->gt, val);

	return intel_gt_debugfs_reset_show(to_gt(i915), val);

}



static int i915_wedged_set(void *data, u64 val)

{

	struct drm_i915_private *i915 = data;



	return intel_gt_debugfs_reset_store(&i915->gt, val);

	return intel_gt_debugfs_reset_store(to_gt(i915), val);

}



DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
@@ -582,7 +582,7 @@ i915_perf_noa_delay_set(void *data, u64 val) 
	 * This would lead to infinite waits as we're doing timestamp

	 * difference on the CS with only 32bits.

	 */

	if (intel_gt_ns_to_clock_interval(&i915->gt, val) > U32_MAX)

	if (intel_gt_ns_to_clock_interval(to_gt(i915), val) > U32_MAX)

		return -EINVAL;



	atomic64_set(&i915->perf.noa_programming_delay, val);
@@ -673,7 +673,7 @@ i915_drop_caches_set(void *data, u64 val) 
	DRM_DEBUG("Dropping caches: 0x%08llx [0x%08llx]\n",

		  val, val & DROP_ALL);



	ret = gt_drop_caches(&i915->gt, val);

	ret = gt_drop_caches(to_gt(i915), val);

	if (ret)

		return ret;
@@ -706,7 +706,7 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, 
static int i915_sseu_status(struct seq_file *m, void *unused)

{

	struct drm_i915_private *i915 = node_to_i915(m->private);

	struct intel_gt *gt = &i915->gt;

	struct intel_gt *gt = to_gt(i915);



	return intel_sseu_status(m, gt);

}
@@ -715,14 +715,14 @@ static int i915_forcewake_open(struct inode *inode, struct file *file) 
{

	struct drm_i915_private *i915 = inode->i_private;



	return intel_gt_pm_debugfs_forcewake_user_open(&i915->gt);

	return intel_gt_pm_debugfs_forcewake_user_open(to_gt(i915));

}



static int i915_forcewake_release(struct inode *inode, struct file *file)

{

	struct drm_i915_private *i915 = inode->i_private;



	return intel_gt_pm_debugfs_forcewake_user_release(&i915->gt);

	return intel_gt_pm_debugfs_forcewake_user_release(to_gt(i915));

}



static const struct file_operations i915_forcewake_fops = {

drivers/gpu/drm/i915/i915_debugfs_params.c

+2 −2
Original line number Diff line number Diff line
@@ -40,8 +40,8 @@ static int notify_guc(struct drm_i915_private *i915) 
{

	int ret = 0;



	if (intel_uc_uses_guc_submission(&i915->gt.uc))

		ret = intel_guc_global_policies_update(&i915->gt.uc.guc);

	if (intel_uc_uses_guc_submission(&to_gt(i915)->uc))

		ret = intel_guc_global_policies_update(&to_gt(i915)->uc.guc);



	return ret;

}

drivers/gpu/drm/i915/i915_drv.c

+16 −16
Original line number Diff line number Diff line
@@ -289,7 +289,7 @@ static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv) 
static void sanitize_gpu(struct drm_i915_private *i915)

{

	if (!INTEL_INFO(i915)->gpu_reset_clobbers_display)

		__intel_gt_reset(&i915->gt, ALL_ENGINES);

		__intel_gt_reset(to_gt(i915), ALL_ENGINES);

}



/**
@@ -312,9 +312,9 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv) 
	intel_device_info_subplatform_init(dev_priv);

	intel_step_init(dev_priv);



	intel_gt_init_early(&dev_priv->gt, dev_priv);

	intel_gt_init_early(to_gt(dev_priv), dev_priv);

	intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);

	intel_uncore_init_early(&dev_priv->uncore, &dev_priv->gt);

	intel_uncore_init_early(&dev_priv->uncore, to_gt(dev_priv));



	spin_lock_init(&dev_priv->irq_lock);

	spin_lock_init(&dev_priv->gpu_error.lock);
@@ -345,7 +345,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv) 


	intel_wopcm_init_early(&dev_priv->wopcm);



	__intel_gt_init_early(&dev_priv->gt, dev_priv);

	__intel_gt_init_early(to_gt(dev_priv), dev_priv);



	i915_gem_init_early(dev_priv);
@@ -366,7 +366,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv) 


err_gem:

	i915_gem_cleanup_early(dev_priv);

	intel_gt_driver_late_release(&dev_priv->gt);

	intel_gt_driver_late_release(to_gt(dev_priv));

	intel_region_ttm_device_fini(dev_priv);

err_ttm:

	vlv_suspend_cleanup(dev_priv);
@@ -385,7 +385,7 @@ static void i915_driver_late_release(struct drm_i915_private *dev_priv) 
	intel_irq_fini(dev_priv);

	intel_power_domains_cleanup(dev_priv);

	i915_gem_cleanup_early(dev_priv);

	intel_gt_driver_late_release(&dev_priv->gt);

	intel_gt_driver_late_release(to_gt(dev_priv));

	intel_region_ttm_device_fini(dev_priv);

	vlv_suspend_cleanup(dev_priv);

	i915_workqueues_cleanup(dev_priv);
@@ -428,7 +428,7 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) 
	intel_setup_mchbar(dev_priv);

	intel_device_info_runtime_init(dev_priv);



	ret = intel_gt_init_mmio(&dev_priv->gt);

	ret = intel_gt_init_mmio(to_gt(dev_priv));

	if (ret)

		goto err_uncore;
@@ -585,9 +585,9 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv) 
	if (ret)

		goto err_ggtt;



	intel_gt_init_hw_early(&dev_priv->gt, &dev_priv->ggtt);

	intel_gt_init_hw_early(to_gt(dev_priv), &dev_priv->ggtt);



	ret = intel_gt_probe_lmem(&dev_priv->gt);

	ret = intel_gt_probe_lmem(to_gt(dev_priv));

	if (ret)

		goto err_mem_regions;
@@ -700,7 +700,7 @@ static void i915_driver_register(struct drm_i915_private *dev_priv) 
	/* Depends on sysfs having been initialized */

	i915_perf_register(dev_priv);



	intel_gt_driver_register(&dev_priv->gt);

	intel_gt_driver_register(to_gt(dev_priv));



	intel_display_driver_register(dev_priv);
@@ -728,7 +728,7 @@ static void i915_driver_unregister(struct drm_i915_private *dev_priv) 


	intel_display_driver_unregister(dev_priv);



	intel_gt_driver_unregister(&dev_priv->gt);

	intel_gt_driver_unregister(to_gt(dev_priv));



	i915_perf_unregister(dev_priv);

	i915_pmu_unregister(dev_priv);
@@ -761,7 +761,7 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv) 
		intel_device_info_print_static(INTEL_INFO(dev_priv), &p);

		intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), &p);

		i915_print_iommu_status(dev_priv, &p);

		intel_gt_info_print(&dev_priv->gt.info, &p);

		intel_gt_info_print(&to_gt(dev_priv)->info, &p);

	}



	if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
@@ -1368,7 +1368,7 @@ static int i915_drm_resume_early(struct drm_device *dev) 


	intel_uncore_resume_early(&dev_priv->uncore);



	intel_gt_check_and_clear_faults(&dev_priv->gt);

	intel_gt_check_and_clear_faults(to_gt(dev_priv));



	intel_display_power_resume_early(dev_priv);
@@ -1550,7 +1550,7 @@ static int intel_runtime_suspend(struct device *kdev) 
	 */

	i915_gem_runtime_suspend(dev_priv);



	intel_gt_runtime_suspend(&dev_priv->gt);

	intel_gt_runtime_suspend(to_gt(dev_priv));



	intel_runtime_pm_disable_interrupts(dev_priv);
@@ -1566,7 +1566,7 @@ static int intel_runtime_suspend(struct device *kdev) 


		intel_runtime_pm_enable_interrupts(dev_priv);



		intel_gt_runtime_resume(&dev_priv->gt);

		intel_gt_runtime_resume(to_gt(dev_priv));



		enable_rpm_wakeref_asserts(rpm);
@@ -1646,7 +1646,7 @@ static int intel_runtime_resume(struct device *kdev) 
	 * No point of rolling back things in case of an error, as the best

	 * we can do is to hope that things will still work (and disable RPM).

	 */

	intel_gt_runtime_resume(&dev_priv->gt);

	intel_gt_runtime_resume(to_gt(dev_priv));



	/*

	 * On VLV/CHV display interrupts are part of the display

drivers/gpu/drm/i915/i915_drv.h

+1 −1
Original line number Diff line number Diff line
@@ -1743,7 +1743,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, 


#define HAS_PXP(dev_priv)  ((IS_ENABLED(CONFIG_DRM_I915_PXP) && \

			    INTEL_INFO(dev_priv)->has_pxp) && \

			    VDBOX_MASK(&dev_priv->gt))

			    VDBOX_MASK(to_gt(dev_priv)))



#define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)

drivers/gpu/drm/i915/i915_gem.c

+8 −8
Original line number Diff line number Diff line
@@ -1049,7 +1049,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv) 
	if (ret)

		return ret;



	intel_uc_fetch_firmwares(&dev_priv->gt.uc);

	intel_uc_fetch_firmwares(&to_gt(dev_priv)->uc);

	intel_wopcm_init(&dev_priv->wopcm);



	ret = i915_init_ggtt(dev_priv);
@@ -1069,7 +1069,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv) 
	 */

	intel_init_clock_gating(dev_priv);



	ret = intel_gt_init(&dev_priv->gt);

	ret = intel_gt_init(to_gt(dev_priv));

	if (ret)

		goto err_unlock;
@@ -1085,7 +1085,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv) 
	i915_gem_drain_workqueue(dev_priv);



	if (ret != -EIO)

		intel_uc_cleanup_firmwares(&dev_priv->gt.uc);

		intel_uc_cleanup_firmwares(&to_gt(dev_priv)->uc);



	if (ret == -EIO) {

		/*
@@ -1093,10 +1093,10 @@ int i915_gem_init(struct drm_i915_private *dev_priv) 
		 * as wedged. But we only want to do this when the GPU is angry,

		 * for all other failure, such as an allocation failure, bail.

		 */

		if (!intel_gt_is_wedged(&dev_priv->gt)) {

		if (!intel_gt_is_wedged(to_gt(dev_priv))) {

			i915_probe_error(dev_priv,

					 "Failed to initialize GPU, declaring it wedged!\n");

			intel_gt_set_wedged(&dev_priv->gt);

			intel_gt_set_wedged(to_gt(dev_priv));

		}



		/* Minimal basic recovery for KMS */
@@ -1127,7 +1127,7 @@ void i915_gem_driver_remove(struct drm_i915_private *dev_priv) 
	intel_wakeref_auto_fini(&dev_priv->ggtt.userfault_wakeref);



	i915_gem_suspend_late(dev_priv);

	intel_gt_driver_remove(&dev_priv->gt);

	intel_gt_driver_remove(to_gt(dev_priv));

	dev_priv->uabi_engines = RB_ROOT;



	/* Flush any outstanding unpin_work. */
@@ -1138,9 +1138,9 @@ void i915_gem_driver_remove(struct drm_i915_private *dev_priv) 


void i915_gem_driver_release(struct drm_i915_private *dev_priv)

{

	intel_gt_driver_release(&dev_priv->gt);

	intel_gt_driver_release(to_gt(dev_priv));



	intel_uc_cleanup_firmwares(&dev_priv->gt.uc);

	intel_uc_cleanup_firmwares(&to_gt(dev_priv)->uc);



	i915_gem_drain_freed_objects(dev_priv);