Commit 2cabc452 authored by Rohit Agarwal's avatar Rohit Agarwal Committed by Bjorn Andersson
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dt-bindings: clock: Add A7 PLL binding for SDX65 



Add information for Cortex A7 PLL clock in Qualcomm
platform SDX65.

Signed-off-by: default avatarRohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: default avatarStephen Boyd <sboyd@kernel.org>
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1645505785-2271-2-git-send-email-quic_rohiagar@quicinc.com
parent 013804a7

Documentation/devicetree/bindings/clock/qcom,a7pll.yaml

+1 −1
Original line number Diff line number Diff line
@@ -10,7 +10,7 @@ maintainers: 
  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>



description:

  The A7 PLL on the Qualcomm platforms like SDX55 is used to provide high

  The A7 PLL on the Qualcomm platforms like SDX55, SDX65 is used to provide high

  frequency clock to the CPU.



properties: