Commit 2c54e184 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'rproc-v5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux 

Pull remoteproc updates from Bjorn Andersson:
 "In the remoteproc core, it's now possible to mark the sysfs attributes
  read only on a per-instance basis, which is then used by the TI wkup
  M3 driver.

  Also, the rproc_shutdown() interface propagates errors to the caller
  and an array underflow is fixed in the debugfs interface. The
  rproc_da_to_va() API is moved to the public API to allow e.g. child
  rpmsg devices to acquire pointers to memory shared with the remote
  processor.

  The TI K3 R5F and DSP drivers gains support for attaching to instances
  already started by the bootloader, aka IPC-only mode.

  The Mediatek remoteproc driver gains support for the MT8186 SCP. The
  driver's probe function is reordered and moved to use the devres
  version of rproc_alloc() to save a few gotos. The driver's probe
  function is also transitioned to use dev_err_probe() to provide better
  debug support.

  Support for the Qualcomm SC7280 Wireless Subsystem (WPSS) is
  introduced. The Hexagon based remoteproc drivers gains support for
  voting for interconnect bandwidth during launch of the remote
  processor. The modem subsystem (MSS) driver gains support for probing
  the BAM-DMUX driver, which provides the network interface towards the
  modem on a set of older Qualcomm platforms. In addition a number a bug
  fixes are introduces in the Qualcomm drivers.

  Lastly Qualcomm ADSP DeviceTree binding is converted to YAML format,
  to allow validation of DeviceTree source files"

* tag 'rproc-v5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux: (22 commits)
  remoteproc: qcom_q6v5_mss: Create platform device for BAM-DMUX
  remoteproc: qcom: q6v5_wpss: Add support for sc7280 WPSS
  dt-bindings: remoteproc: qcom: Add SC7280 WPSS support
  dt-bindings: remoteproc: qcom: adsp: Convert binding to YAML
  remoteproc: k3-dsp: Add support for IPC-only mode for all K3 DSPs
  remoteproc: k3-dsp: Refactor mbox request code in start
  remoteproc: k3-r5: Add support for IPC-only mode for all R5Fs
  remoteproc: k3-r5: Refactor mbox request code in start
  remoteproc: Change rproc_shutdown() to return a status
  remoteproc: qcom: q6v5: Add interconnect path proxy vote
  remoteproc: mediatek: Support mt8186 scp
  dt-bindings: remoteproc: mediatek: Add binding for mt8186 scp
  remoteproc: qcom_q6v5_mss: Fix some leaks in q6v5_alloc_memory_region
  remoteproc: qcom_wcnss: Add missing of_node_put() in wcnss_alloc_memory_region
  remoteproc: qcom: Fix missing of_node_put in adsp_alloc_memory_region
  remoteproc: move rproc_da_to_va declaration to remoteproc.h
  remoteproc: wkup_m3: Set sysfs_read_only flag
  remoteproc: Introduce sysfs_read_only flag
  remoteproc: Fix count check in rproc_coredump_write()
  remoteproc: mtk_scp: Use dev_err_probe() where possible
  ...
parents d177850d 59983c74

Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml

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@@ -17,6 +17,7 @@ properties: 
  compatible:

    enum:

      - mediatek,mt8183-scp

      - mediatek,mt8186-scp

      - mediatek,mt8192-scp

      - mediatek,mt8195-scp

Documentation/devicetree/bindings/remoteproc/qcom,hexagon-v56.txt

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Qualcomm Technology Inc. Hexagon v56 Peripheral Image Loader



This document defines the binding for a component that loads and boots firmware

on the Qualcomm Technology Inc. Hexagon v56 core.



- compatible:

	Usage: required

	Value type: <string>

	Definition: must be one of:

		    "qcom,qcs404-cdsp-pil",

		    "qcom,sdm845-adsp-pil"



- reg:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: must specify the base address and size of the qdsp6ss register



- interrupts-extended:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: must list the watchdog, fatal IRQs ready, handover and

		    stop-ack IRQs



- interrupt-names:

	Usage: required

	Value type: <stringlist>

	Definition: must be "wdog", "fatal", "ready", "handover", "stop-ack"



- clocks:

	Usage: required

	Value type: <prop-encoded-array>

	Definition:  List of phandles and clock specifier pairs for the Hexagon,

		     per clock-names below.



- clock-names:

	Usage: required for SDM845 ADSP

	Value type: <stringlist>

	Definition: List of clock input name strings sorted in the same

		    order as the clocks property. Definition must have

		    "xo", "sway_cbcr", "lpass_ahbs_aon_cbcr",

		    "lpass_ahbm_aon_cbcr", "qdsp6ss_xo", "qdsp6ss_sleep"

		    and "qdsp6ss_core".



- clock-names:

	Usage: required for QCS404 CDSP

	Value type: <stringlist>

	Definition: List of clock input name strings sorted in the same

		    order as the clocks property. Definition must have

		    "xo", "sway", "tbu", "bimc", "ahb_aon", "q6ss_slave",

		    "q6ss_master", "q6_axim".



- power-domains:

	Usage: required

	Value type: <phandle>

	Definition: reference to cx power domain node.



- resets:

	Usage: required

	Value type: <phandle>

	Definition: reference to the list of resets for the Hexagon.



- reset-names:

        Usage: required for SDM845 ADSP

        Value type: <stringlist>

        Definition: must be "pdc_sync" and "cc_lpass"



- reset-names:

        Usage: required for QCS404 CDSP

        Value type: <stringlist>

        Definition: must be "restart"



- qcom,halt-regs:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: a phandle reference to a syscon representing TCSR followed

		    by the offset within syscon for Hexagon halt register.



- memory-region:

	Usage: required

	Value type: <phandle>

	Definition: reference to the reserved-memory for the firmware



- qcom,smem-states:

	Usage: required

	Value type: <phandle>

	Definition: reference to the smem state for requesting the Hexagon to

		    shut down



- qcom,smem-state-names:

	Usage: required

	Value type: <stringlist>

	Definition: must be "stop"





= SUBNODES

The adsp node may have an subnode named "glink-edge" that describes the

communication edge, channels and devices related to the Hexagon.

See ../soc/qcom/qcom,glink.txt for details on how to describe these.



= EXAMPLE

The following example describes the resources needed to boot control the

ADSP, as it is found on SDM845 boards.



	remoteproc@17300000 {

		compatible = "qcom,sdm845-adsp-pil";

		reg = <0x17300000 0x40c>;



		interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,

			<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,

			<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,

			<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,

			<&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;

		interrupt-names = "wdog", "fatal", "ready",

			"handover", "stop-ack";



		clocks = <&rpmhcc RPMH_CXO_CLK>,

			<&gcc GCC_LPASS_SWAY_CLK>,

			<&lpasscc LPASS_Q6SS_AHBS_AON_CLK>,

			<&lpasscc LPASS_Q6SS_AHBM_AON_CLK>,

			<&lpasscc LPASS_QDSP6SS_XO_CLK>,

			<&lpasscc LPASS_QDSP6SS_SLEEP_CLK>,

			<&lpasscc LPASS_QDSP6SS_CORE_CLK>;

		clock-names = "xo", "sway_cbcr",

			"lpass_ahbs_aon_cbcr",

			"lpass_ahbm_aon_cbcr", "qdsp6ss_xo",

			"qdsp6ss_sleep", "qdsp6ss_core";



		power-domains = <&rpmhpd SDM845_CX>;



		resets = <&pdc_reset PDC_AUDIO_SYNC_RESET>,

			 <&aoss_reset AOSS_CC_LPASS_RESTART>;

		reset-names = "pdc_sync", "cc_lpass";



		qcom,halt-regs = <&tcsr_mutex_regs 0x22000>;



		memory-region = <&pil_adsp_mem>;



		qcom,smem-states = <&adsp_smp2p_out 0>;

		qcom,smem-state-names = "stop";

	};

Documentation/devicetree/bindings/remoteproc/qcom,qcs404-cdsp-pil.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/remoteproc/qcom,qcs404-cdsp-pil.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm QCS404 CDSP Peripheral Image Loader



maintainers:

  - Bjorn Andersson <bjorn.andersson@linaro.org>



description:

  This document defines the binding for a component that loads and boots firmware

  on the Qualcomm Technology Inc. CDSP (Compute DSP).



properties:

  compatible:

    enum:

      - qcom,qcs404-cdsp-pil



  reg:

    maxItems: 1

    description:

      The base address and size of the qdsp6ss register



  interrupts:

    items:

      - description: Watchdog interrupt

      - description: Fatal interrupt

      - description: Ready interrupt

      - description: Handover interrupt

      - description: Stop acknowledge interrupt



  interrupt-names:

    items:

      - const: wdog

      - const: fatal

      - const: ready

      - const: handover

      - const: stop-ack



  clocks:

    items:

      - description: XO clock

      - description: SWAY clock

      - description: TBU clock

      - description: BIMC clock

      - description: AHB AON clock

      - description: Q6SS SLAVE clock

      - description: Q6SS MASTER clock

      - description: Q6 AXIM clock



  clock-names:

    items:

      - const: xo

      - const: sway

      - const: tbu

      - const: bimc

      - const: ahb_aon

      - const: q6ss_slave

      - const: q6ss_master

      - const: q6_axim



  power-domains:

    items:

      - description: CX power domain



  resets:

    items:

      - description: AOSS restart



  reset-names:

    items:

      - const: restart



  memory-region:

    maxItems: 1

    description: Reference to the reserved-memory for the Hexagon core



  qcom,halt-regs:

    $ref: /schemas/types.yaml#/definitions/phandle-array

    description:

      Phandle reference to a syscon representing TCSR followed by the

      three offsets within syscon for q6, modem and nc halt registers.



  qcom,smem-states:

    $ref: /schemas/types.yaml#/definitions/phandle-array

    description: States used by the AP to signal the Hexagon core

    items:

      - description: Stop the modem



  qcom,smem-state-names:

    $ref: /schemas/types.yaml#/definitions/string

    description: The names of the state bits used for SMP2P output

    items:

      - const: stop



required:

  - compatible

  - reg

  - interrupts

  - interrupt-names

  - clocks

  - clock-names

  - power-domains

  - resets

  - reset-names

  - qcom,halt-regs

  - memory-region

  - qcom,smem-states

  - qcom,smem-state-names



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/clock/qcom,gcc-qcs404.h>

    #include <dt-bindings/power/qcom-rpmpd.h>

    #include <dt-bindings/clock/qcom,turingcc-qcs404.h>

    remoteproc@b00000 {

        compatible = "qcom,qcs404-cdsp-pil";

        reg = <0x00b00000 0x4040>;



        interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,

                              <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,

                              <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,

                              <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,

                              <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;

        interrupt-names = "wdog", "fatal", "ready",

                          "handover", "stop-ack";



        clocks = <&xo_board>,

                 <&gcc GCC_CDSP_CFG_AHB_CLK>,

                 <&gcc GCC_CDSP_TBU_CLK>,

                 <&gcc GCC_BIMC_CDSP_CLK>,

                 <&turingcc TURING_WRAPPER_AON_CLK>,

                 <&turingcc TURING_Q6SS_AHBS_AON_CLK>,

                 <&turingcc TURING_Q6SS_AHBM_AON_CLK>,

                 <&turingcc TURING_Q6SS_Q6_AXIM_CLK>;

        clock-names = "xo",

                      "sway",

                      "tbu",

                      "bimc",

                      "ahb_aon",

                      "q6ss_slave",

                      "q6ss_master",

                      "q6_axim";



        power-domains = <&rpmhpd SDM845_CX>;



        resets = <&gcc GCC_CDSP_RESTART>;

        reset-names = "restart";



        qcom,halt-regs = <&tcsr 0x19004>;



        memory-region = <&cdsp_fw_mem>;



        qcom,smem-states = <&cdsp_smp2p_out 0>;

        qcom,smem-state-names = "stop";

    };

Documentation/devicetree/bindings/remoteproc/qcom,sc7280-wpss-pil.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/remoteproc/qcom,sc7280-wpss-pil.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm SC7280 WPSS Peripheral Image Loader



maintainers:

  - Bjorn Andersson <bjorn.andersson@linaro.org>



description:

  This document defines the binding for a component that loads and boots firmware

  on the Qualcomm Technology Inc. WPSS.



properties:

  compatible:

    enum:

      - qcom,sc7280-wpss-pil



  reg:

    maxItems: 1

    description:

      The base address and size of the qdsp6ss register



  interrupts:

    items:

      - description: Watchdog interrupt

      - description: Fatal interrupt

      - description: Ready interrupt

      - description: Handover interrupt

      - description: Stop acknowledge interrupt

      - description: Shutdown acknowledge interrupt



  interrupt-names:

    items:

      - const: wdog

      - const: fatal

      - const: ready

      - const: handover

      - const: stop-ack

      - const: shutdown-ack



  clocks:

    items:

      - description: GCC WPSS AHB BDG Master clock

      - description: GCC WPSS AHB clock

      - description: GCC WPSS RSCP clock

      - description: XO clock



  clock-names:

    items:

      - const: ahb_bdg

      - const: ahb

      - const: rscp

      - const: xo



  power-domains:

    items:

      - description: CX power domain

      - description: MX power domain



  power-domain-names:

    items:

      - const: cx

      - const: mx



  resets:

    items:

      - description: AOSS restart

      - description: PDC SYNC



  reset-names:

    items:

      - const: restart

      - const: pdc_sync



  memory-region:

    $ref: /schemas/types.yaml#/definitions/phandle

    description: Reference to the reserved-memory for the Hexagon core



  firmware-name:

    $ref: /schemas/types.yaml#/definitions/string

    description:

      The name of the firmware which should be loaded for this remote

      processor.



  qcom,halt-regs:

    $ref: /schemas/types.yaml#/definitions/phandle-array

    description:

      Phandle reference to a syscon representing TCSR followed by the

      three offsets within syscon for q6, modem and nc halt registers.



  qcom,qmp:

    $ref: /schemas/types.yaml#/definitions/phandle

    description: Reference to the AOSS side-channel message RAM.



  qcom,smem-states:

    $ref: /schemas/types.yaml#/definitions/phandle-array

    description: States used by the AP to signal the Hexagon core

    items:

      - description: Stop the modem



  qcom,smem-state-names:

    $ref: /schemas/types.yaml#/definitions/string

    description: The names of the state bits used for SMP2P output

    items:

      - const: stop



  glink-edge:

    type: object

    description: |

      Qualcomm G-Link subnode which represents communication edge, channels

      and devices related to the ADSP.



    properties:

      interrupts:

        items:

          - description: IRQ from WPSS to GLINK



      mboxes:

        items:

          - description: Mailbox for communication between APPS and WPSS



      label:

        description: The names of the state bits used for SMP2P output

        items:

          - const: wpss



      qcom,remote-pid:

        $ref: /schemas/types.yaml#/definitions/uint32

        description: ID of the shared memory used by GLINK for communication with WPSS

        maxItems: 1



    required:

      - interrupts

      - mboxes

      - label

      - qcom,remote-pid



    additionalProperties: false



required:

  - compatible

  - reg

  - interrupts

  - interrupt-names

  - clocks

  - clock-names

  - power-domains

  - power-domain-names

  - resets

  - reset-names

  - qcom,halt-regs

  - memory-region

  - qcom,qmp

  - qcom,smem-states

  - qcom,smem-state-names

  - glink-edge



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/clock/qcom,gcc-sc7280.h>

    #include <dt-bindings/clock/qcom,rpmh.h>

    #include <dt-bindings/power/qcom-rpmpd.h>

    #include <dt-bindings/reset/qcom,sdm845-aoss.h>

    #include <dt-bindings/reset/qcom,sdm845-pdc.h>

    #include <dt-bindings/mailbox/qcom-ipcc.h>

    remoteproc@8a00000 {

        compatible = "qcom,sc7280-wpss-pil";

        reg = <0x08a00000 0x10000>;



        interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,

                              <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,

                              <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,

                              <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,

                              <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,

                              <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;

        interrupt-names = "wdog", "fatal", "ready", "handover",

                          "stop-ack", "shutdown-ack";



        clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>,

                 <&gcc GCC_WPSS_AHB_CLK>,

                 <&gcc GCC_WPSS_RSCP_CLK>,

                 <&rpmhcc RPMH_CXO_CLK>;

        clock-names = "ahb_bdg", "ahb",

                      "rscp", "xo";



        power-domains = <&rpmhpd SC7280_CX>,

                        <&rpmhpd SC7280_MX>;

        power-domain-names = "cx", "mx";



        memory-region = <&wpss_mem>;



        qcom,qmp = <&aoss_qmp>;



        qcom,smem-states = <&wpss_smp2p_out 0>;

        qcom,smem-state-names = "stop";



        resets = <&aoss_reset AOSS_CC_WCSS_RESTART>,

                 <&pdc_reset PDC_WPSS_SYNC_RESET>;

        reset-names = "restart", "pdc_sync";



        qcom,halt-regs = <&tcsr_mutex 0x37000>;



        glink-edge {

            interrupts-extended = <&ipcc IPCC_CLIENT_WPSS

                                         IPCC_MPROC_SIGNAL_GLINK_QMP

                                         IRQ_TYPE_EDGE_RISING>;

            mboxes = <&ipcc IPCC_CLIENT_WPSS

                            IPCC_MPROC_SIGNAL_GLINK_QMP>;



            label = "wpss";

            qcom,remote-pid = <13>;

        };

    };

Documentation/devicetree/bindings/remoteproc/qcom,sdm845-adsp-pil.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/remoteproc/qcom,sdm845-adsp-pil.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm SDM845 ADSP Peripheral Image Loader



maintainers:

  - Bjorn Andersson <bjorn.andersson@linaro.org>



description:

  This document defines the binding for a component that loads and boots firmware

  on the Qualcomm Technology Inc. ADSP.



properties:

  compatible:

    enum:

      - qcom,sdm845-adsp-pil



  reg:

    maxItems: 1

    description:

      The base address and size of the qdsp6ss register



  interrupts:

    items:

      - description: Watchdog interrupt

      - description: Fatal interrupt

      - description: Ready interrupt

      - description: Handover interrupt

      - description: Stop acknowledge interrupt



  interrupt-names:

    items:

      - const: wdog

      - const: fatal

      - const: ready

      - const: handover

      - const: stop-ack



  clocks:

    items:

      - description: XO clock

      - description: SWAY clock

      - description: LPASS AHBS AON clock

      - description: LPASS AHBM AON clock

      - description: QDSP XO clock

      - description: Q6SP6SS SLEEP clock

      - description: Q6SP6SS CORE clock



  clock-names:

    items:

      - const: xo

      - const: sway_cbcr

      - const: lpass_ahbs_aon_cbcr

      - const: lpass_ahbm_aon_cbcr

      - const: qdsp6ss_xo

      - const: qdsp6ss_sleep

      - const: qdsp6ss_core



  power-domains:

    items:

      - description: CX power domain



  resets:

    items:

      - description: PDC AUDIO SYNC RESET

      - description: CC LPASS restart



  reset-names:

    items:

      - const: pdc_sync

      - const: cc_lpass



  memory-region:

    maxItems: 1

    description: Reference to the reserved-memory for the Hexagon core



  qcom,halt-regs:

    $ref: /schemas/types.yaml#/definitions/phandle-array

    description:

      Phandle reference to a syscon representing TCSR followed by the

      three offsets within syscon for q6, modem and nc halt registers.



  qcom,smem-states:

    $ref: /schemas/types.yaml#/definitions/phandle-array

    description: States used by the AP to signal the Hexagon core

    items:

      - description: Stop the modem



  qcom,smem-state-names:

    $ref: /schemas/types.yaml#/definitions/string

    description: The names of the state bits used for SMP2P output

    items:

      - const: stop



required:

  - compatible

  - reg

  - interrupts

  - interrupt-names

  - clocks

  - clock-names

  - power-domains

  - resets

  - reset-names

  - qcom,halt-regs

  - memory-region

  - qcom,smem-states

  - qcom,smem-state-names



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/clock/qcom,rpmh.h>

    #include <dt-bindings/clock/qcom,gcc-sdm845.h>

    #include <dt-bindings/clock/qcom,lpass-sdm845.h>

    #include <dt-bindings/power/qcom-rpmpd.h>

    #include <dt-bindings/reset/qcom,sdm845-pdc.h>

    #include <dt-bindings/reset/qcom,sdm845-aoss.h>

    remoteproc@17300000 {

        compatible = "qcom,sdm845-adsp-pil";

        reg = <0x17300000 0x40c>;



        interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,

                <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,

                <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,

                <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,

                <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;

        interrupt-names = "wdog", "fatal", "ready",

                "handover", "stop-ack";



        clocks = <&rpmhcc RPMH_CXO_CLK>,

                 <&gcc GCC_LPASS_SWAY_CLK>,

                 <&lpasscc LPASS_Q6SS_AHBS_AON_CLK>,

                 <&lpasscc LPASS_Q6SS_AHBM_AON_CLK>,

                 <&lpasscc LPASS_QDSP6SS_XO_CLK>,

                 <&lpasscc LPASS_QDSP6SS_SLEEP_CLK>,

                 <&lpasscc LPASS_QDSP6SS_CORE_CLK>;

        clock-names = "xo", "sway_cbcr",

                "lpass_ahbs_aon_cbcr",

                "lpass_ahbm_aon_cbcr", "qdsp6ss_xo",

                "qdsp6ss_sleep", "qdsp6ss_core";



        power-domains = <&rpmhpd SDM845_CX>;



        resets = <&pdc_reset PDC_AUDIO_SYNC_RESET>,

                 <&aoss_reset AOSS_CC_LPASS_RESTART>;

        reset-names = "pdc_sync", "cc_lpass";



        qcom,halt-regs = <&tcsr_mutex_regs 0x22000>;



        memory-region = <&pil_adsp_mem>;



        qcom,smem-states = <&adsp_smp2p_out 0>;

        qcom,smem-state-names = "stop";

    };