Commit 2c26cb4d authored by Claudiu Beznea's avatar Claudiu Beznea Committed by Nicolas Ferre
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ARM: at91: pm: add sama7g5 ddr controller 



Add SAMA7G5 DDR controller to the list of DDR controller compatibles.
At the moment there is no standby support. Adapt the code for this.

Signed-off-by: default avatarClaudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: default avatarNicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20210415105010.569620-18-claudiu.beznea@microchip.com
parent 5b0bef87

arch/arm/mach-at91/pm.c

+6 −3
Original line number Diff line number Diff line
@@ -548,6 +548,7 @@ static const struct of_device_id ramc_ids[] __initconst = { 
	{ .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] },

	{ .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] },

	{ .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] },

	{ .compatible = "microchip,sama7g5-uddrc", },

	{ /*sentinel*/ }

};
@@ -565,9 +566,11 @@ static __init void at91_dt_ramc(void) 
			panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);



		ramc = of_id->data;

		if (ramc) {

			if (!standby)

				standby = ramc->idle;

			soc_pm.data.memctrl = ramc->memctrl;

		}



		idx++;

	}