Commit 2c0a284c authored by Ashutosh Dixit's avatar Ashutosh Dixit Committed by Rodrigo Vivi
Browse files

drm/i915/rps: Prefer REG_FIELD_GET in intel_rps_get_cagf 



Instead of masks/shifts settle on REG_FIELD_GET as the standard way to
extract reg fields. This allows future patches touching this code to also
consistently use REG_FIELD_GET and friends.

Suggested-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarAshutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarBadal Nilawar <badal.nilawar@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221114123348.3474216-2-badal.nilawar@intel.com
parent b186b2d9

drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c

+1 −1
Original line number Diff line number Diff line
@@ -307,7 +307,7 @@ void intel_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *p) 
		drm_printf(p, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>

			   MEMSTAT_VID_SHIFT);

		drm_printf(p, "Current P-state: %d\n",

			   (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);

			   REG_FIELD_GET(MEMSTAT_PSTATE_MASK, rgvstat));

	} else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {

		u32 rpmodectl, freq_sts;

drivers/gpu/drm/i915/gt/intel_gt_regs.h

+4 −8
Original line number Diff line number Diff line
@@ -799,12 +799,9 @@ 
#define GEN6_RP_DOWN_TIMEOUT			_MMIO(0xa010)

#define GEN6_RP_INTERRUPT_LIMITS		_MMIO(0xa014)

#define GEN6_RPSTAT1				_MMIO(0xa01c)

#define   GEN6_CAGF_SHIFT			8

#define   HSW_CAGF_SHIFT			7

#define   GEN9_CAGF_SHIFT			23

#define   GEN6_CAGF_MASK			(0x7f << GEN6_CAGF_SHIFT)

#define   HSW_CAGF_MASK				(0x7f << HSW_CAGF_SHIFT)

#define   GEN9_CAGF_MASK			(0x1ff << GEN9_CAGF_SHIFT)

#define   GEN6_CAGF_MASK			REG_GENMASK(14, 8)

#define   HSW_CAGF_MASK				REG_GENMASK(13, 7)

#define   GEN9_CAGF_MASK			REG_GENMASK(31, 23)

#define GEN6_RP_CONTROL				_MMIO(0xa024)

#define   GEN6_RP_MEDIA_TURBO			(1 << 11)

#define   GEN6_RP_MEDIA_MODE_MASK		(3 << 9)
@@ -1376,8 +1373,7 @@ 
#define MEMSTAT_ILK				_MMIO(0x111f8)

#define   MEMSTAT_VID_MASK			0x7f00

#define   MEMSTAT_VID_SHIFT			8

#define   MEMSTAT_PSTATE_MASK			0x00f8

#define   MEMSTAT_PSTATE_SHIFT			3

#define   MEMSTAT_PSTATE_MASK			REG_GENMASK(7, 3)

#define   MEMSTAT_MON_ACTV			(1 << 2)

#define   MEMSTAT_SRC_CTL_MASK			0x0003

#define   MEMSTAT_SRC_CTL_CORE			0

drivers/gpu/drm/i915/gt/intel_rps.c

+5 −6
Original line number Diff line number Diff line
@@ -2080,16 +2080,15 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat) 
	u32 cagf;



	if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))

		cagf = (rpstat >> 8) & 0xff;

		cagf = REG_FIELD_GET(RPE_MASK, rpstat);

	else if (GRAPHICS_VER(i915) >= 9)

		cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;

		cagf = REG_FIELD_GET(GEN9_CAGF_MASK, rpstat);

	else if (IS_HASWELL(i915) || IS_BROADWELL(i915))

		cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;

		cagf = REG_FIELD_GET(HSW_CAGF_MASK, rpstat);

	else if (GRAPHICS_VER(i915) >= 6)

		cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;

		cagf = REG_FIELD_GET(GEN6_CAGF_MASK, rpstat);

	else

		cagf = gen5_invert_freq(rps, (rpstat & MEMSTAT_PSTATE_MASK) >>

					MEMSTAT_PSTATE_SHIFT);

		cagf = gen5_invert_freq(rps, REG_FIELD_GET(MEMSTAT_PSTATE_MASK, rpstat));



	return cagf;

}