Commit 2bae03a6 authored by Peter Wang's avatar Peter Wang Committed by Martin K. Petersen
Browse files

scsi: ufs: ufs-mediatek: Prevent host hang by setting CLK_CG early 

Some UFSHCI hosts in MediaTek UFS platform need workaround to prevent host
hang issue by setting CLK_CG bit before host is enabled.

This operation shall have no side effect on those platforms which do not
support this bit.

Link: https://lore.kernel.org/r/20220623035052.18802-4-stanley.chu@mediatek.com


Reviewed-by: default avatarStanley Chu <stanley.chu@mediatek.com>
Reviewed-by: default avatarBart Van Assche <bvanassche@acm.org>
Signed-off-by: default avatarPeter Wang <peter.wang@mediatek.com>
Signed-off-by: default avatarStanley Chu <stanley.chu@mediatek.com>
Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parent 981b4ac0

drivers/ufs/host/ufs-mediatek.c

+8 −0
Original line number Original line Diff line number Diff line
@@ -183,6 +183,14 @@ static int ufs_mtk_hce_enable_notify(struct ufs_hba *hba, 
			hba->capabilities &= ~MASK_AUTO_HIBERN8_SUPPORT;

			hba->capabilities &= ~MASK_AUTO_HIBERN8_SUPPORT;

			hba->ahit = 0;

			hba->ahit = 0;

		}

		}



		/*

		 * Turn on CLK_CG early to bypass abnormal ERR_CHK signal

		 * to prevent host hang issue

		 */

		ufshcd_writel(hba,

			      ufshcd_readl(hba, REG_UFS_XOUFS_CTRL) | 0x80,

			      REG_UFS_XOUFS_CTRL);

	}

	}





	return 0;

	return 0;

drivers/ufs/host/ufs-mediatek.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -12,6 +12,7 @@ 
/*

/*

 * Vendor specific UFSHCI Registers

 * Vendor specific UFSHCI Registers

 */

 */

#define REG_UFS_XOUFS_CTRL          0x140

#define REG_UFS_REFCLK_CTRL         0x144

#define REG_UFS_REFCLK_CTRL         0x144

#define REG_UFS_EXTREG              0x2100

#define REG_UFS_EXTREG              0x2100

#define REG_UFS_MPHYCTRL            0x2200

#define REG_UFS_MPHYCTRL            0x2200