Commit 2b9d7b65 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2023-08-10' of git://anongit.freedesktop.org/drm/drm-intel into drm-next 



- Display SDVO fixes (Juha-Pekka, Jani)
- Taking Stolen handling out of FBC code (Jouni)
- Replace acronym with full platform name in defines (Dnyaneshwar, A\
nusha)
- Display IRQ cleanups (Jani)
- Initialize display version numbers (Luca)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ZNVAR53jmvA1p6D5@intel.com
parents e6b17f5c 129ebb54

drivers/gpu/drm/i915/display/icl_dsi.c

+3 −2
Original line number Diff line number Diff line
@@ -444,7 +444,8 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder) 
		intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);



		/* For EHL, TGL, set latency optimization for PCS_DW1 lanes */

		if (IS_JSL_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >= 12)) {

		if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv) ||

		    (DISPLAY_VER(dev_priv) >= 12)) {

			intel_de_rmw(dev_priv, ICL_PORT_PCS_DW1_AUX(phy),

				     LATENCY_OPTIM_MASK, LATENCY_OPTIM_VAL(0));
@@ -553,7 +554,7 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder, 
		}

	}



	if (IS_JSL_EHL(dev_priv)) {

	if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {

		for_each_dsi_phy(phy, intel_dsi->phys)

			intel_de_rmw(dev_priv, ICL_DPHY_CHKN(phy),

				     0, ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP);

drivers/gpu/drm/i915/display/intel_cdclk.c

+7 −7
Original line number Diff line number Diff line
@@ -470,7 +470,7 @@ static void hsw_get_cdclk(struct drm_i915_private *dev_priv, 
		cdclk_config->cdclk = 450000;

	else if (freq == LCPLL_CLK_FREQ_450)

		cdclk_config->cdclk = 450000;

	else if (IS_HSW_ULT(dev_priv))

	else if (IS_HASWELL_ULT(dev_priv))

		cdclk_config->cdclk = 337500;

	else

		cdclk_config->cdclk = 540000;
@@ -3155,7 +3155,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) 
 */

void intel_update_max_cdclk(struct drm_i915_private *dev_priv)

{

	if (IS_JSL_EHL(dev_priv)) {

	if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {

		if (dev_priv->display.cdclk.hw.ref == 24000)

			dev_priv->display.cdclk.max_cdclk_freq = 552000;

		else
@@ -3200,9 +3200,9 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv) 
		 */

		if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)

			dev_priv->display.cdclk.max_cdclk_freq = 450000;

		else if (IS_BDW_ULX(dev_priv))

		else if (IS_BROADWELL_ULX(dev_priv))

			dev_priv->display.cdclk.max_cdclk_freq = 450000;

		else if (IS_BDW_ULT(dev_priv))

		else if (IS_BROADWELL_ULT(dev_priv))

			dev_priv->display.cdclk.max_cdclk_freq = 540000;

		else

			dev_priv->display.cdclk.max_cdclk_freq = 675000;
@@ -3567,10 +3567,10 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) 
		dev_priv->display.cdclk.table = dg2_cdclk_table;

	} else if (IS_ALDERLAKE_P(dev_priv)) {

		/* Wa_22011320316:adl-p[a0] */

		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {

		if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {

			dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;

			dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;

		} else if (IS_ADLP_RPLU(dev_priv)) {

		} else if (IS_RAPTORLAKE_U(dev_priv)) {

			dev_priv->display.cdclk.table = rplu_cdclk_table;

			dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs;

		} else {
@@ -3583,7 +3583,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) 
	} else if (DISPLAY_VER(dev_priv) >= 12) {

		dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;

		dev_priv->display.cdclk.table = icl_cdclk_table;

	} else if (IS_JSL_EHL(dev_priv)) {

	} else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {

		dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs;

		dev_priv->display.cdclk.table = icl_cdclk_table;

	} else if (DISPLAY_VER(dev_priv) >= 11) {

drivers/gpu/drm/i915/display/intel_combo_phy.c

+4 −3
Original line number Diff line number Diff line
@@ -141,7 +141,7 @@ static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy) 


	if (IS_ALDERLAKE_S(i915))

		return phy == PHY_A;

	else if (IS_JSL_EHL(i915) ||

	else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) ||

		 IS_ROCKETLAKE(i915) ||

		 IS_DG1(i915))

		return phy < PHY_C;
@@ -242,7 +242,7 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv, 
		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),

				     IREFGEN, IREFGEN);



		if (IS_JSL_EHL(dev_priv)) {

		if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {

			if (ehl_vbt_ddi_d_present(dev_priv))

				expected_val = ICL_PHY_MISC_MUX_DDID;
@@ -333,7 +333,8 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv) 
		 * "internal" child devices.

		 */

		val = intel_de_read(dev_priv, ICL_PHY_MISC(phy));

		if (IS_JSL_EHL(dev_priv) && phy == PHY_A) {

		if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) &&

		    phy == PHY_A) {

			val &= ~ICL_PHY_MISC_MUX_DDID;



			if (ehl_vbt_ddi_d_present(dev_priv))

drivers/gpu/drm/i915/display/intel_ddi.c

+4 −3
Original line number Diff line number Diff line
@@ -3583,7 +3583,8 @@ void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, 
{

	if (DISPLAY_VER(dev_priv) >= 12 && crtc_state->port_clock > 594000)

		crtc_state->min_voltage_level = 2;

	else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000)

	else if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) &&

		 crtc_state->port_clock > 594000)

		crtc_state->min_voltage_level = 3;

	else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000)

		crtc_state->min_voltage_level = 1;
@@ -4878,7 +4879,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, 
		encoder->disable_clock = dg1_ddi_disable_clock;

		encoder->is_clock_enabled = dg1_ddi_is_clock_enabled;

		encoder->get_config = dg1_ddi_get_config;

	} else if (IS_JSL_EHL(dev_priv)) {

	} else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {

		if (intel_ddi_is_tc(dev_priv, port)) {

			encoder->enable_clock = jsl_ddi_tc_enable_clock;

			encoder->disable_clock = jsl_ddi_tc_disable_clock;
@@ -4949,7 +4950,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, 
		encoder->hpd_pin = rkl_hpd_pin(dev_priv, port);

	else if (DISPLAY_VER(dev_priv) >= 12)

		encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);

	else if (IS_JSL_EHL(dev_priv))

	else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))

		encoder->hpd_pin = ehl_hpd_pin(dev_priv, port);

	else if (DISPLAY_VER(dev_priv) == 11)

		encoder->hpd_pin = icl_hpd_pin(dev_priv, port);

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

+5 −5
Original line number Diff line number Diff line
@@ -1410,7 +1410,7 @@ tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder, 
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);



	if (crtc_state->port_clock > 270000) {

		if (IS_TGL_UY(dev_priv)) {

		if (IS_TIGERLAKE_UY(dev_priv)) {

			return intel_get_buf_trans(&tgl_uy_combo_phy_trans_dp_hbr2,

						   n_entries);

		} else {
@@ -1740,15 +1740,15 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder) 
			encoder->get_buf_trans = icl_get_mg_buf_trans;

	} else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {

		encoder->get_buf_trans = bxt_get_buf_trans;

	} else if (IS_CML_ULX(i915) || IS_CFL_ULX(i915) || IS_KBL_ULX(i915)) {

	} else if (IS_COMETLAKE_ULX(i915) || IS_COFFEELAKE_ULX(i915) || IS_KABYLAKE_ULX(i915)) {

		encoder->get_buf_trans = kbl_y_get_buf_trans;

	} else if (IS_CML_ULT(i915) || IS_CFL_ULT(i915) || IS_KBL_ULT(i915)) {

	} else if (IS_COMETLAKE_ULT(i915) || IS_COFFEELAKE_ULT(i915) || IS_KABYLAKE_ULT(i915)) {

		encoder->get_buf_trans = kbl_u_get_buf_trans;

	} else if (IS_COMETLAKE(i915) || IS_COFFEELAKE(i915) || IS_KABYLAKE(i915)) {

		encoder->get_buf_trans = kbl_get_buf_trans;

	} else if (IS_SKL_ULX(i915)) {

	} else if (IS_SKYLAKE_ULX(i915)) {

		encoder->get_buf_trans = skl_y_get_buf_trans;

	} else if (IS_SKL_ULT(i915)) {

	} else if (IS_SKYLAKE_ULT(i915)) {

		encoder->get_buf_trans = skl_u_get_buf_trans;

	} else if (IS_SKYLAKE(i915)) {

		encoder->get_buf_trans = skl_get_buf_trans;