Commit 2b922a9d authored by Dan Williams's avatar Dan Williams
Browse files

cxl/registers: Fix Documentation warning 



Commit 0f06157e ("cxl/core: Move register mapping infrastructure")
neglected to add a DOC header for the new drivers/core/regs.c file.

Reported-by: default avatarBen Widawsky <ben.widawsky@intel.com>
Reviewed-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/163072206675.2250120.3527179192933919995.stgit@dwillia2-desk3.amr.corp.intel.com


Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
parent a01da6ca

Documentation/driver-api/cxl/memory-devices.rst

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@@ -43,7 +43,7 @@ CXL Core 
   :doc: cxl pmem



.. kernel-doc:: drivers/cxl/core/regs.c

   :internal:

   :doc: cxl registers



External Interfaces

===================

drivers/cxl/core/regs.c

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// SPDX-License-Identifier: GPL-2.0-only

/* Copyright(c) 2020 Intel Corporation. */



#include <linux/io-64-nonatomic-lo-hi.h>

#include <linux/device.h>

#include <linux/slab.h>

#include <linux/pci.h>

#include <cxlmem.h>



/**

 * DOC: cxl registers

 *

 * CXL device capabilities are enumerated by PCI DVSEC (Designated

 * Vendor-specific) and / or descriptors provided by platform firmware.

 * They can be defined as a set like the device and component registers

 * mandated by CXL Section 8.1.12.2 Memory Device PCIe Capabilities and

 * Extended Capabilities, or they can be individual capabilities

 * appended to bridged and endpoint devices.

 *

 * Provide common infrastructure for enumerating and mapping these

 * discrete capabilities.

 */



/**

 * cxl_probe_component_regs() - Detect CXL Component register blocks

 * @dev: Host device of the @base mapping