Unverified Commit 2b884797 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
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!15454 RDMA/hns: Fix mbox timing out by adding retry mechanism 

Merge Pull Request from: @ci-robot 
 
PR sync from: Junxian Huang <huangjunxian6@hisilicon.com>
https://mailweb.openeuler.org/archives/list/kernel@openeuler.org/message/WNIU6Q34FAXDL6OMAJWYBKRZMKXG35ZN/ 
 
https://gitee.com/openeuler/kernel/issues/IBSLDS 
 
Link:https://gitee.com/openeuler/kernel/pulls/15454

 

Reviewed-by: default avatarChengchang Tang <tangchengchang@huawei.com>
Reviewed-by: default avatarLi Nan <linan122@huawei.com>
Signed-off-by: default avatarLi Nan <linan122@huawei.com>
parents ed789a9f ec8607a6

drivers/infiniband/hw/hns/hns_roce_hw_v2.c

+48 −16
Original line number Diff line number Diff line
@@ -1395,10 +1395,8 @@ static u32 hns_roce_cmdq_tx_timeout(u16 opcode, u32 tx_timeout) 
	return tx_timeout;

}



static void hns_roce_wait_csq_done(struct hns_roce_dev *hr_dev, u16 opcode)

static void hns_roce_wait_csq_done(struct hns_roce_dev *hr_dev, u32 tx_timeout)

{

	struct hns_roce_v2_priv *priv = hr_dev->priv;

	u32 tx_timeout = hns_roce_cmdq_tx_timeout(opcode, priv->cmq.tx_timeout);

	u32 timeout = 0;



	do {
@@ -1408,8 +1406,9 @@ static void hns_roce_wait_csq_done(struct hns_roce_dev *hr_dev, u16 opcode) 
	} while (++timeout < tx_timeout);

}



static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev,

			       struct hns_roce_cmq_desc *desc, int num)

static int __hns_roce_cmq_send_one(struct hns_roce_dev *hr_dev,

				   struct hns_roce_cmq_desc *desc,

				   int num, u32 tx_timeout)

{

	struct hns_roce_v2_priv *priv = hr_dev->priv;

	struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
@@ -1418,8 +1417,6 @@ static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 
	int ret;

	int i;



	spin_lock_bh(&csq->lock);



	tail = csq->head;



	for (i = 0; i < num; i++) {
@@ -1433,22 +1430,17 @@ static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 


	atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CMDS_CNT]);



	hns_roce_wait_csq_done(hr_dev, le16_to_cpu(desc->opcode));

	hns_roce_wait_csq_done(hr_dev, tx_timeout);

	if (hns_roce_cmq_csq_done(hr_dev)) {

		ret = 0;

		for (i = 0; i < num; i++) {

			/* check the result of hardware write back */

			desc[i] = csq->desc[tail++];

			desc_ret = le16_to_cpu(csq->desc[tail++].retval);

			if (tail == csq->desc_num)

				tail = 0;



			desc_ret = le16_to_cpu(desc[i].retval);

			if (likely(desc_ret == CMD_EXEC_SUCCESS))

				continue;



			dev_err_ratelimited(hr_dev->dev,

					    "Cmdq IO error, opcode = 0x%x, return = 0x%x.\n",

					    desc->opcode, desc_ret);

			ret = hns_roce_cmd_err_convert_errno(desc_ret);

		}

	} else {
@@ -1463,10 +1455,50 @@ static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 
		ret = -EAGAIN;

	}



	if (ret)

		atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CMDS_ERR_CNT]);



	return ret;

}



static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev,

			       struct hns_roce_cmq_desc *desc, int num)

{

	struct hns_roce_v2_priv *priv = hr_dev->priv;

	struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;

	u16 opcode = le16_to_cpu(desc->opcode);

	u32 tx_timeout = hns_roce_cmdq_tx_timeout(opcode, priv->cmq.tx_timeout);

	u8 try_cnt = HNS_ROCE_OPC_POST_MB_TRY_CNT;

	u32 rsv_tail;

	int ret;

	int i;



	while (try_cnt) {

		try_cnt--;



		spin_lock_bh(&csq->lock);

		rsv_tail = csq->head;

		ret = __hns_roce_cmq_send_one(hr_dev, desc, num, tx_timeout);

		if (opcode == HNS_ROCE_OPC_POST_MB && ret == -ETIME &&

		    try_cnt) {

			spin_unlock_bh(&csq->lock);

			mdelay(HNS_ROCE_OPC_POST_MB_RETRY_GAP_MSEC);

			continue;

		}



		for (i = 0; i < num; i++) {

			desc[i] = csq->desc[rsv_tail++];

			if (rsv_tail == csq->desc_num)

				rsv_tail = 0;

		}

		spin_unlock_bh(&csq->lock);

		break;

	}



	if (ret)

		atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CMDS_ERR_CNT]);

		dev_err_ratelimited(hr_dev->dev,

				    "Cmdq IO error, opcode = 0x%x, return = %d.\n",

				    opcode, ret);



	return ret;

}

drivers/infiniband/hw/hns/hns_roce_hw_v2.h

+2 −0
Original line number Diff line number Diff line
@@ -243,6 +243,8 @@ enum hns_roce_opcode_type { 
};



#define HNS_ROCE_OPC_POST_MB_TIMEOUT 35000

#define HNS_ROCE_OPC_POST_MB_TRY_CNT 8

#define HNS_ROCE_OPC_POST_MB_RETRY_GAP_MSEC 5

struct hns_roce_cmdq_tx_timeout_map {

	u16 opcode;

	u32 tx_timeout;