Commit 2b8175a1 authored by Sai Prakash Ranjan's avatar Sai Prakash Ranjan Committed by Bjorn Andersson
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soc: qcom: llcc: Add write-cache cacheable support 



Newer SoCs with LLCC IP version 2.1.0.0 and later support write
sub-cache cacheable feature. Use a separate llcc_slice_config member
"write_scid_cacheable_en" to identify this feature and program
LLCC_TRP_SCID_WRSC_CACHEABLE_EN register to enable it.

Signed-off-by: default avatarSai Prakash Ranjan <quic_saipraka@quicinc.com>
Tested-by: default avatarVinod Koul <vkoul@kernel.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/83372c8178f579d055ec58212ce5af5d55abadd4.1643355594.git.quic_saipraka@quicinc.com
parent 8008e790

drivers/soc/qcom/llcc-qcom.c

+15 −0
Original line number Diff line number Diff line
@@ -51,10 +51,12 @@ 
#define LLCC_TRP_SCID_DIS_CAP_ALLOC   0x21f00

#define LLCC_TRP_PCB_ACT              0x21f04

#define LLCC_TRP_WRSC_EN              0x21f20

#define LLCC_TRP_WRSC_CACHEABLE_EN    0x21f2c



#define BANK_OFFSET_STRIDE	      0x80000



#define LLCC_VERSION_2_0_0_0          0x02000000

#define LLCC_VERSION_2_1_0_0          0x02010000



/**

 * struct llcc_slice_config - Data associated with the llcc slice
@@ -80,6 +82,8 @@ 
 *               collapse.

 * @activate_on_init: Activate the slice immediately after it is programmed

 * @write_scid_en: Bit enables write cache support for a given scid.

 * @write_scid_cacheable_en: Enables write cache cacheable support for a

 *			     given scid (not supported on v2 or older hardware).

 */

struct llcc_slice_config {

	u32 usecase_id;
@@ -95,6 +99,7 @@ struct llcc_slice_config { 
	bool retain_on_pc;

	bool activate_on_init;

	bool write_scid_en;

	bool write_scid_cacheable_en;

};



struct qcom_llcc_config {
@@ -515,6 +520,16 @@ static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config, 
			return ret;

	}



	if (drv_data->version >= LLCC_VERSION_2_1_0_0) {

		u32 wr_cache_en;



		wr_cache_en = config->write_scid_cacheable_en << config->slice_id;

		ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_WRSC_CACHEABLE_EN,

					 BIT(config->slice_id), wr_cache_en);

		if (ret)

			return ret;

	}



	if (config->activate_on_init) {

		desc.slice_id = config->slice_id;

		ret = llcc_slice_activate(&desc);