Commit 2b5cc851 authored by Chris Ball's avatar Chris Ball
Browse files

Revert "dts: socfpga: Add support for SD/MMC on the SOCFPGA platform" 

This reverts commit d9c3f5df, which
should not have been merged via mmc-next.  It's in arm-soc instead now.
parent b42b9b12

Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt

deleted100644 → 0
+0 −23
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* Altera SOCFPGA specific extensions to the Synopsys Designware Mobile

  Storage Host Controller



The Synopsys designware mobile storage host controller is used to interface

a SoC with storage medium such as eMMC or SD/MMC cards. This file documents

differences between the core Synopsys dw mshc controller properties described

by synopsys-dw-mshc.txt and the properties used by the Altera SOCFPGA specific

extensions to the Synopsys Designware Mobile Storage Host Controller.



Required Properties:



* compatible: should be

	- "altr,socfpga-dw-mshc": for Altera's SOCFPGA platform



Example:



	mmc: dwmmc0@ff704000 {

		compatible = "altr,socfpga-dw-mshc";

		reg = <0xff704000 0x1000>;

		interrupts = <0 129 4>;

		#address-cells = <1>;

		#size-cells = <0>;

	};

arch/arm/boot/dts/socfpga.dtsi

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@@ -473,17 +473,6 @@ 
			arm,data-latency = <2 1 1>;

		};



		mmc: dwmmc0@ff704000 {

			compatible = "altr,socfpga-dw-mshc";

			reg = <0xff704000 0x1000>;

			interrupts = <0 139 4>;

			fifo-depth = <0x400>;

			#address-cells = <1>;

			#size-cells = <0>;

			clocks = <&l4_mp_clk>, <&sdmmc_clk>;

			clock-names = "biu", "ciu";

		};



		/* Local timer */

		timer@fffec600 {

			compatible = "arm,cortex-a9-twd-timer";
@@ -538,7 +527,7 @@ 
		};



		sysmgr@ffd08000 {

			compatible = "altr,sys-mgr", "syscon";

				compatible = "altr,sys-mgr";

				reg = <0xffd08000 0x4000>;

			};

	};

arch/arm/boot/dts/socfpga_arria5.dtsi

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@@ -27,17 +27,6 @@ 
			};

		};



		dwmmc0@ff704000 {

			num-slots = <1>;

			supports-highspeed;

			broken-cd;



			slot@0 {

				reg = <0>;

				bus-width = <4>;

			};

		};



		serial0@ffc02000 {

			clock-frequency = <100000000>;

		};

arch/arm/boot/dts/socfpga_cyclone5.dtsi

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@@ -28,17 +28,6 @@ 
			};

		};



		dwmmc0@ff704000 {

			num-slots = <1>;

			supports-highspeed;

			broken-cd;



			slot@0 {

				reg = <0>;

				bus-width = <4>;

			};

		};



		ethernet@ff702000 {

			phy-mode = "rgmii";

			phy-addr = <0xffffffff>; /* probe for phy addr */

arch/arm/boot/dts/socfpga_vt.dts

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@@ -41,17 +41,6 @@ 
			};

		};



		dwmmc0@ff704000 {

			num-slots = <1>;

			supports-highspeed;

			broken-cd;



			slot@0 {

				reg = <0>;

				bus-width = <4>;

			};

		};



		ethernet@ff700000 {

			phy-mode = "gmii";

			status = "okay";