Commit 2b5a4562 authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915/display: Simplify GLK display version tests 



GLK has always been a bit of a special case since it reports INTEL_GEN()
as 9, but has version 10 display IP.  Now we can properly represent the
display version as 10 and simplify the display generation tests
throughout the display code.

Aside from manually adding the version to the glk_info structure, the
rest of this patch is generated with a Coccinelle semantic patch.  Note
that we also need to switch any code that matches gen10 today but *not*
GLK to be CNL-specific:

        @@ expression dev_priv; @@
        - DISPLAY_VER(dev_priv) > 9
        + DISPLAY_VER(dev_priv) >= 10

        @@ expression dev_priv, E; @@
        (
        - DISPLAY_VER(dev_priv) >= 10 && E
        + (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) && E
        |
        - DISPLAY_VER(dev_priv) >= 10
        + DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)
        |
        - IS_DISPLAY_RANGE(dev_priv, 10, E)
        + IS_DISPLAY_RANGE(dev_priv, 11, E) || IS_CANNONLAKE(dev_priv)
        )

        @@ expression dev_priv, E, E2; @@
        (
        - (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
        + IS_DISPLAY_VER(dev_priv, 10)
        |
        - E || IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)
        + E || IS_DISPLAY_VER(dev_priv, 10)
        |
        - (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv))
        + IS_DISPLAY_VER(dev_priv, 10)
        |
        - IS_GEMINILAKE(dev_priv) || E || IS_CANNONLAKE(dev_priv)
        + E || IS_DISPLAY_VER(dev_priv, 10)
        |
        - E || IS_GEMINILAKE(dev_priv) || E2 || IS_CANNONLAKE(dev_priv)
        + E || E2 || IS_DISPLAY_VER(dev_priv, 10)
        |
        - (IS_DISPLAY_VER(dev_priv, 10) || IS_GEMINILAKE(dev_priv))
        + IS_DISPLAY_VER(dev_priv, 10)
        |
        - (IS_GEMINILAKE(dev_priv) || IS_DISPLAY_VER(dev_priv, 10))
        + IS_DISPLAY_VER(dev_priv, 10)
        )

        @@ expression dev_priv; @@
        - (IS_DISPLAY_VER(dev_priv, 9) && !IS_GEMINILAKE(dev_priv))
        + IS_DISPLAY_VER(dev_priv, 9)

        @@ expression dev_priv; @@
        (
        - !(DISPLAY_VER(dev_priv) >= 11 || IS_DISPLAY_VER(dev_priv, 10))
        + DISPLAY_VER(dev_priv) < 10
        |
        - (DISPLAY_VER(dev_priv) >= 11 || IS_DISPLAY_VER(dev_priv, 10))
        + DISPLAY_VER(dev_priv) >= 10
        )

        @@ expression dev_priv, E; @@
        - E || DISPLAY_VER(dev_priv) >= 11 || IS_DISPLAY_VER(dev_priv, 10)
        + E || DISPLAY_VER(dev_priv) >= 10

        @@ expression dev_priv, E; @@
        - (IS_DISPLAY_RANGE(dev_priv, 11, E) || IS_DISPLAY_VER(dev_priv, 10))
        + IS_DISPLAY_RANGE(dev_priv, 10, E)

        @@ expression dev_priv; @@
        (
        - DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv) || IS_GEN9_LP(dev_priv)
        + DISPLAY_VER(dev_priv) >= 10 || IS_GEN9_LP(dev_priv)
        |
        - IS_GEN9_LP(dev_priv) || DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)
        + IS_GEN9_LP(dev_priv) || DISPLAY_VER(dev_priv) >= 10
        )

        @@ expression dev_priv, E; @@
        - !(DISPLAY_VER(dev_priv) >= E)
        + DISPLAY_VER(dev_priv) < E

v2:
 - Convert gen10 conditions that don't include GLK into CNL conditions.
   (Ville)

v3:
 - Rework coccinelle rules so that "ver>=10" turns into "ver>=11||is_cnl." (Ville)

v3.1:
 - Manually re-add the ".display.version = 10" to glk_info after
   regenerating patch via Coccinelle.

v4:
 - Also apply cocci rules to intel_pm.c and i915_irq.c!  (CI)

Cc: Ville Syrjälä <ville.syrjala@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210322233840.4056851-1-matthew.d.roper@intel.com
parent 373abf1a

drivers/gpu/drm/i915/display/intel_atomic.c

+3 −4
Original line number Diff line number Diff line
@@ -332,8 +332,7 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta 
	    plane_state->hw.fb->format->is_yuv &&

	    plane_state->hw.fb->format->num_planes > 1) {

		struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

		if (IS_DISPLAY_VER(dev_priv, 9) &&

		    !IS_GEMINILAKE(dev_priv)) {

		if (IS_DISPLAY_VER(dev_priv, 9)) {

			mode = SKL_PS_SCALER_MODE_NV12;

		} else if (icl_is_hdr_plane(dev_priv, plane->id)) {

			/*
@@ -351,7 +350,7 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta 
			if (linked)

				mode |= PS_PLANE_Y_SEL(linked->id);

		}

	} else if (DISPLAY_VER(dev_priv) > 9 || IS_GEMINILAKE(dev_priv)) {

	} else if (DISPLAY_VER(dev_priv) >= 10) {

		mode = PS_SCALER_MODE_NORMAL;

	} else if (num_scalers_need == 1 && intel_crtc->num_scalers > 1) {

		/*
@@ -460,7 +459,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, 
				 * isn't necessary to change between HQ and dyn mode

				 * on those platforms.

				 */

				if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))

				if (DISPLAY_VER(dev_priv) >= 10)

					continue;



				plane = drm_plane_from_index(&dev_priv->drm, i);

drivers/gpu/drm/i915/display/intel_audio.c

+1 −1
Original line number Diff line number Diff line
@@ -1022,7 +1022,7 @@ static unsigned long i915_audio_component_get_power(struct device *kdev) 
		if (IS_GEMINILAKE(dev_priv))

			glk_force_audio_cdclk(dev_priv, true);



		if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))

		if (DISPLAY_VER(dev_priv) >= 10)

			intel_de_write(dev_priv, AUD_PIN_BUF_CTL,

				       (intel_de_read(dev_priv, AUD_PIN_BUF_CTL) | AUD_PIN_BUF_ENABLE));

	}

drivers/gpu/drm/i915/display/intel_bios.c

+1 −2
Original line number Diff line number Diff line
@@ -917,8 +917,7 @@ parse_psr(struct drm_i915_private *i915, const struct bdb_header *bdb) 
	 * Old decimal value is wake up time in multiples of 100 us.

	 */

	if (bdb->version >= 205 &&

	    (IS_GEN9_BC(i915) || IS_GEMINILAKE(i915) ||

	     DISPLAY_VER(i915) >= 10)) {

	    (IS_GEN9_BC(i915) || DISPLAY_VER(i915) >= 10)) {

		switch (psr_table->tp1_wakeup_time) {

		case 0:

			i915->vbt.psr.tp1_wakeup_time_us = 500;

drivers/gpu/drm/i915/display/intel_cdclk.c

+14 −12
Original line number Diff line number Diff line
@@ -1397,7 +1397,7 @@ static void bxt_de_pll_readout(struct drm_i915_private *dev_priv, 
	 * CNL+ have the ratio directly in the PLL enable register, gen9lp had

	 * it in a separate PLL control register.

	 */

	if (DISPLAY_VER(dev_priv) >= 10)

	if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))

		ratio = val & CNL_CDCLK_PLL_RATIO_MASK;

	else

		ratio = intel_de_read(dev_priv, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
@@ -1433,7 +1433,7 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv, 
		break;

	case BXT_CDCLK_CD2X_DIV_SEL_1_5:

		drm_WARN(&dev_priv->drm,

			 IS_GEMINILAKE(dev_priv) || DISPLAY_VER(dev_priv) >= 10,

			 DISPLAY_VER(dev_priv) >= 10,

			 "Unsupported divider\n");

		div = 3;

		break;
@@ -1441,7 +1441,8 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv, 
		div = 4;

		break;

	case BXT_CDCLK_CD2X_DIV_SEL_4:

		drm_WARN(&dev_priv->drm, DISPLAY_VER(dev_priv) >= 10,

		drm_WARN(&dev_priv->drm,

			 DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv),

			 "Unsupported divider\n");

		div = 8;

		break;
@@ -1558,7 +1559,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, 
	int ret;



	/* Inform power controller of upcoming frequency change. */

	if (DISPLAY_VER(dev_priv) >= 10)

	if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))

		ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,

					SKL_CDCLK_PREPARE_FOR_CHANGE,

					SKL_CDCLK_READY_FOR_CHANGE,
@@ -1591,7 +1592,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, 
		break;

	case 3:

		drm_WARN(&dev_priv->drm,

			 IS_GEMINILAKE(dev_priv) || DISPLAY_VER(dev_priv) >= 10,

			 DISPLAY_VER(dev_priv) >= 10,

			 "Unsupported divider\n");

		divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;

		break;
@@ -1599,13 +1600,14 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, 
		divider = BXT_CDCLK_CD2X_DIV_SEL_2;

		break;

	case 8:

		drm_WARN(&dev_priv->drm, DISPLAY_VER(dev_priv) >= 10,

		drm_WARN(&dev_priv->drm,

			 DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv),

			 "Unsupported divider\n");

		divider = BXT_CDCLK_CD2X_DIV_SEL_4;

		break;

	}



	if (DISPLAY_VER(dev_priv) >= 10) {

	if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {

		if (dev_priv->cdclk.hw.vco != 0 &&

		    dev_priv->cdclk.hw.vco != vco)

			cnl_cdclk_pll_disable(dev_priv);
@@ -1636,7 +1638,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, 
	if (pipe != INVALID_PIPE)

		intel_wait_for_vblank(dev_priv, pipe);



	if (DISPLAY_VER(dev_priv) >= 10) {

	if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {

		ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,

					      cdclk_config->voltage_level);

	} else {
@@ -1661,7 +1663,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, 


	intel_update_cdclk(dev_priv);



	if (DISPLAY_VER(dev_priv) >= 10)

	if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))

		/*

		 * Can't read out the voltage level :(

		 * Let's just assume everything is as expected.
@@ -1998,7 +2000,7 @@ static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state) 
	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);

	int pixel_rate = crtc_state->pixel_rate;



	if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))

	if (DISPLAY_VER(dev_priv) >= 10)

		return DIV_ROUND_UP(pixel_rate, 2);

	else if (IS_DISPLAY_VER(dev_priv, 9) ||

		 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
@@ -2048,7 +2050,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) 
	    crtc_state->has_audio &&

	    crtc_state->port_clock >= 540000 &&

	    crtc_state->lane_count == 4) {

		if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {

		if (IS_DISPLAY_VER(dev_priv, 10)) {

			/* Display WA #1145: glk,cnl */

			min_cdclk = max(316800, min_cdclk);

		} else if (IS_DISPLAY_VER(dev_priv, 9) || IS_BROADWELL(dev_priv)) {
@@ -2588,7 +2590,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) 
{

	int max_cdclk_freq = dev_priv->max_cdclk_freq;



	if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))

	if (DISPLAY_VER(dev_priv) >= 10)

		return 2 * max_cdclk_freq;

	else if (IS_DISPLAY_VER(dev_priv, 9) ||

		 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))

drivers/gpu/drm/i915/display/intel_color.c

+4 −4
Original line number Diff line number Diff line
@@ -737,7 +737,7 @@ static void ivb_load_lut_ext_max(const struct intel_crtc_state *crtc_state) 
	 * ToDo: Extend the ABI to be able to program values

	 * from 3.0 to 7.0

	 */

	if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {

	if (DISPLAY_VER(dev_priv) >= 10) {

		intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 0),

				    1 << 16);

		intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 1),
@@ -1711,7 +1711,7 @@ int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_stat 
	} else {

		if (DISPLAY_VER(dev_priv) >= 11)

			return icl_gamma_precision(crtc_state);

		else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))

		else if (IS_DISPLAY_VER(dev_priv, 10))

			return glk_gamma_precision(crtc_state);

		else if (IS_IRONLAKE(dev_priv))

			return ilk_gamma_precision(crtc_state);
@@ -2119,7 +2119,7 @@ void intel_color_init(struct intel_crtc *crtc) 
	} else {

		if (DISPLAY_VER(dev_priv) >= 11)

			dev_priv->display.color_check = icl_color_check;

		else if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))

		else if (DISPLAY_VER(dev_priv) >= 10)

			dev_priv->display.color_check = glk_color_check;

		else if (DISPLAY_VER(dev_priv) >= 7)

			dev_priv->display.color_check = ivb_color_check;
@@ -2136,7 +2136,7 @@ void intel_color_init(struct intel_crtc *crtc) 
		if (DISPLAY_VER(dev_priv) >= 11) {

			dev_priv->display.load_luts = icl_load_luts;

			dev_priv->display.read_luts = icl_read_luts;

		} else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {

		} else if (IS_DISPLAY_VER(dev_priv, 10)) {

			dev_priv->display.load_luts = glk_load_luts;

			dev_priv->display.read_luts = glk_read_luts;

		} else if (DISPLAY_VER(dev_priv) >= 8) {