Commit 2b47d54e authored by Rich Felker's avatar Rich Felker
Browse files

sh: add J2 atomics using the cas.l instruction 



Signed-off-by: default avatarRich Felker <dalias@libc.org>
parent 834da197

arch/sh/include/asm/atomic.h

+8 −0
Original line number Diff line number Diff line 
#ifndef __ASM_SH_ATOMIC_H

#define __ASM_SH_ATOMIC_H



#if defined(CONFIG_CPU_J2)



#include <asm-generic/atomic.h>



#else



/*

 * Atomic operations that C can't guarantee us.  Useful for

 * resource counting etc..
@@ -63,4 +69,6 @@ static inline int __atomic_add_unless(atomic_t *v, int a, int u) 
	return c;

}



#endif /* CONFIG_CPU_J2 */



#endif /* __ASM_SH_ATOMIC_H */

arch/sh/include/asm/barrier.h

+5 −0
Original line number Diff line number Diff line
@@ -29,6 +29,11 @@ 
#define wmb()		mb()

#define ctrl_barrier()	__icbi(PAGE_OFFSET)

#else

#if defined(CONFIG_CPU_J2) && defined(CONFIG_SMP)

#define __smp_mb()	do { int tmp = 0; __asm__ __volatile__ ("cas.l %0,%0,@%1" : "+r"(tmp) : "z"(&tmp) : "memory", "t"); } while(0)

#define __smp_rmb()	__smp_mb()

#define __smp_wmb()	__smp_mb()

#endif

#define ctrl_barrier()	__asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop")

#endif

arch/sh/include/asm/bitops-cas.h

0 → 100644
+93 −0
Original line number Diff line number Diff line 
#ifndef __ASM_SH_BITOPS_CAS_H

#define __ASM_SH_BITOPS_CAS_H



static inline unsigned __bo_cas(volatile unsigned *p, unsigned old, unsigned new)

{

	__asm__ __volatile__("cas.l %1,%0,@r0"

		: "+r"(new)

		: "r"(old), "z"(p)

		: "t", "memory" );

	return new;

}



static inline void set_bit(int nr, volatile void *addr)

{

	unsigned mask, old;

	volatile unsigned *a = addr;



	a += nr >> 5;

	mask = 1U << (nr & 0x1f);



	do old = *a;

	while (__bo_cas(a, old, old|mask) != old);

}



static inline void clear_bit(int nr, volatile void *addr)

{

	unsigned mask, old;

	volatile unsigned *a = addr;



	a += nr >> 5;

	mask = 1U << (nr & 0x1f);



	do old = *a;

	while (__bo_cas(a, old, old&~mask) != old);

}



static inline void change_bit(int nr, volatile void *addr)

{

	unsigned mask, old;

	volatile unsigned *a = addr;



	a += nr >> 5;

	mask = 1U << (nr & 0x1f);



	do old = *a;

	while (__bo_cas(a, old, old^mask) != old);

}



static inline int test_and_set_bit(int nr, volatile void *addr)

{

	unsigned mask, old;

	volatile unsigned *a = addr;



	a += nr >> 5;

	mask = 1U << (nr & 0x1f);



	do old = *a;

	while (__bo_cas(a, old, old|mask) != old);



	return !!(old & mask);

}



static inline int test_and_clear_bit(int nr, volatile void *addr)

{

	unsigned mask, old;

	volatile unsigned *a = addr;



	a += nr >> 5;

	mask = 1U << (nr & 0x1f);



	do old = *a;

	while (__bo_cas(a, old, old&~mask) != old);



	return !!(old & mask);

}



static inline int test_and_change_bit(int nr, volatile void *addr)

{

	unsigned mask, old;

	volatile unsigned *a = addr;



	a += nr >> 5;

	mask = 1U << (nr & 0x1f);



	do old = *a;

	while (__bo_cas(a, old, old^mask) != old);



	return !!(old & mask);

}



#include <asm-generic/bitops/non-atomic.h>



#endif /* __ASM_SH_BITOPS_CAS_H */

arch/sh/include/asm/bitops.h

+2 −0
Original line number Diff line number Diff line
@@ -18,6 +18,8 @@ 
#include <asm/bitops-op32.h>

#elif defined(CONFIG_CPU_SH4A)

#include <asm/bitops-llsc.h>

#elif defined(CONFIG_CPU_J2) && defined(CONFIG_SMP)

#include <asm/bitops-cas.h>

#else

#include <asm-generic/bitops/atomic.h>

#include <asm-generic/bitops/non-atomic.h>

arch/sh/include/asm/cmpxchg-cas.h

0 → 100644
+24 −0
Original line number Diff line number Diff line 
#ifndef __ASM_SH_CMPXCHG_CAS_H

#define __ASM_SH_CMPXCHG_CAS_H



static inline unsigned long

__cmpxchg_u32(volatile u32 *m, unsigned long old, unsigned long new)

{

	__asm__ __volatile__("cas.l %1,%0,@r0"

		: "+r"(new)

		: "r"(old), "z"(m)

		: "t", "memory" );

	return new;

}



static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val)

{

	unsigned long old;

	do old = *m;

	while (__cmpxchg_u32(m, old, val) != old);

	return old;

}



#include <asm/cmpxchg-xchg.h>



#endif /* __ASM_SH_CMPXCHG_CAS_H */