Unverified Commit 2b28c9e0 authored Apr 18, 2022 by Tianfei zhang Committed by Xu Yilun May 10, 2022

Documentation: fpga: dfl: add link address of feature id table



This patch adds the link address of feature id table in documentation.

Signed-off-by: Tianfei zhang <tianfei.zhang@intel.com>
Reviewed-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Acked-by: Moritz Fischer <mdf@kernel.org>
Acked-by: Wu Hao <hao.wu@intel.com>
Link: https://lore.kernel.org/r/20220419032942.427429-3-tianfei.zhang@intel.com


Signed-off-by: Xu Yilun <yilun.xu@intel.com>

parent 88b3f3ff

Documentation/fpga/dfl.rst

+5 −0

Original line number	Diff line number	Diff line
		@@ -502,6 +502,11 @@ Developer only needs to provide a sub feature driver with matched feature id.
		FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c)
		could be a reference.

		Please refer to below link to existing feature id table and guide for new feature
		ids application.
		https://github.com/OPAE/dfl-feature-id


		Location of DFLs on a PCI Device
		================================
		The original method for finding a DFL on a PCI device assumed the start of the