Commit 2b073994 authored by Binbin Wu's avatar Binbin Wu Committed by Zhiquan Li
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KVM: x86/mmu: Drop non-PA bits when getting GFN for guest's PGD 

mainline inclusion
from mainline-v6.8-rc1
commit a130066f74008858ac425b7497d231742474a0ea
category: feature
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I94GWL
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=a130066f74008858ac425b7497d231742474a0ea



--------------------------------

Drop non-PA bits when getting GFN for guest's PGD with the maximum theoretical
mask for guest MAXPHYADDR.

Do it unconditionally because it's harmless for 32-bit guests, querying 64-bit
mode would be more expensive, and for EPT the mask isn't tied to guest mode.
Using PT_BASE_ADDR_MASK would be technically wrong (PAE paging has 64-bit
elements _except_ for CR3, which has only 32 valid bits), it wouldn't matter
in practice though.

Opportunistically use GENMASK_ULL() to define __PT_BASE_ADDR_MASK.

Intel-SIG: commit a130066f7400 KVM: x86/mmu: Drop non-PA bits when
getting GFN for guest's PGD
Backport KVM Linear Address Masking (LAM) support.

Signed-off-by: default avatarBinbin Wu <binbin.wu@linux.intel.com>
Tested-by: default avatarXuelian Guo <xuelian.guo@intel.com>
Link: https://lore.kernel.org/r/20230913124227.12574-6-binbin.wu@linux.intel.com


Signed-off-by: default avatarSean Christopherson <seanjc@google.com>
[ Zhiquan Li: amend commit log ]
Signed-off-by: default avatarZhiquan Li <zhiquan1.li@intel.com>
parent 0428f6d0

arch/x86/kvm/mmu/mmu.c

+1 −1
Original line number Diff line number Diff line
@@ -3774,7 +3774,7 @@ static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) 
	hpa_t root;



	root_pgd = kvm_mmu_get_guest_pgd(vcpu, mmu);

	root_gfn = root_pgd >> PAGE_SHIFT;

	root_gfn = (root_pgd & __PT_BASE_ADDR_MASK) >> PAGE_SHIFT;



	if (!kvm_vcpu_is_visible_gfn(vcpu, root_gfn)) {

		mmu->root.hpa = kvm_mmu_get_dummy_root();

arch/x86/kvm/mmu/mmu_internal.h

+1 −0
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ 
#endif



/* Page table builder macros common to shadow (host) PTEs and guest PTEs. */

#define __PT_BASE_ADDR_MASK GENMASK_ULL(51, 12)

#define __PT_LEVEL_SHIFT(level, bits_per_level)	\

	(PAGE_SHIFT + ((level) - 1) * (bits_per_level))

#define __PT_INDEX(address, level, bits_per_level) \

arch/x86/kvm/mmu/paging_tmpl.h

+1 −1
Original line number Diff line number Diff line
@@ -62,7 +62,7 @@ 
#endif



/* Common logic, but per-type values.  These also need to be undefined. */

#define PT_BASE_ADDR_MASK	((pt_element_t)(((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)))

#define PT_BASE_ADDR_MASK	((pt_element_t)__PT_BASE_ADDR_MASK)

#define PT_LVL_ADDR_MASK(lvl)	__PT_LVL_ADDR_MASK(PT_BASE_ADDR_MASK, lvl, PT_LEVEL_BITS)

#define PT_LVL_OFFSET_MASK(lvl)	__PT_LVL_OFFSET_MASK(PT_BASE_ADDR_MASK, lvl, PT_LEVEL_BITS)

#define PT_INDEX(addr, lvl)	__PT_INDEX(addr, lvl, PT_LEVEL_BITS)