Commit 2b062ed4 authored Aug 15, 2023 by Marc Zyngier

arm64: Add missing BRB/CFP/DVP/CPP instructions



HFGITR_EL2 traps a bunch of instructions for which we don't have
encodings yet. Add them.

Reviewed-by: Miguel Luis <miguel.luis@oracle.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Jing Zhang <jingzhangos@google.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20230815183903.2735724-8-maz@kernel.org

parent 57596c8f

arch/arm64/include/asm/sysreg.h

+7 −0

Original line number	Diff line number	Diff line
		@@ -735,6 +735,13 @@
		#define OP_TLBI_VALE2NXS sys_insn(1, 4, 9, 7, 5)
		#define OP_TLBI_VMALLS12E1NXS sys_insn(1, 4, 9, 7, 6)

		/* Misc instructions */
		#define OP_BRB_IALL sys_insn(1, 1, 7, 2, 4)
		#define OP_BRB_INJ sys_insn(1, 1, 7, 2, 5)
		#define OP_CFP_RCTX sys_insn(1, 3, 7, 3, 4)
		#define OP_DVP_RCTX sys_insn(1, 3, 7, 3, 5)
		#define OP_CPP_RCTX sys_insn(1, 3, 7, 3, 7)

		/* Common SCTLR_ELx flags. */
		#define SCTLR_ELx_ENTP2 (BIT(60))
		#define SCTLR_ELx_DSSBS (BIT(44))