Commit 2af3e53a authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2023-04-21' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "This is the regular and hopefully last round of fixes for 6.3.

  Pretty small, a few amdgpu, one i915, one nouveau, one rockchip and
  one gpu scheduler fix:

  nouveau:
   - fix dma-resv timeout

  rockchip:
   - fix suspend/resume

  sched:
   - fix timeout handling

  i915:
   - Fix fast wake AUX sync len

  amdgpu:
   - GPU reset fix
   - DCN 3.1.5 line buffer fix
   - Display fix for single channel memory configs
   - Fix a possible divide by 0"

* tag 'drm-fixes-2023-04-21' of git://anongit.freedesktop.org/drm/drm:
  drm/amd/display: fix a divided-by-zero error
  drm/amd/display: limit timing for single dimm memory
  drm/amd/display: set dcn315 lb bpp to 48
  drm/amdgpu: Fix desktop freezed after gpu-reset
  drm/rockchip: vop2: Use regcache_sync() to fix suspend/resume
  drm/nouveau: fix incorrect conversion to dma_resv_wait_timeout()
  drm/rockchip: vop2: fix suspend/resume
  drm/i915: Fix fast wake AUX sync len
  drm/sched: Check scheduler ready before calling timeout handling
parents b7bc77e2 00a4bd00

drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c

+3 −0
Original line number Original line Diff line number Diff line
@@ -596,6 +596,9 @@ int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 
	if (!src->enabled_types || !src->funcs->set)

	if (!src->enabled_types || !src->funcs->set)

		return -EINVAL;

		return -EINVAL;





	if (WARN_ON(!amdgpu_irq_enabled(adev, src, type)))

		return -EINVAL;



	if (atomic_dec_and_test(&src->enabled_types[type]))

	if (atomic_dec_and_test(&src->enabled_types[type]))

		return amdgpu_irq_update(adev, src, type);

		return amdgpu_irq_update(adev, src, type);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

+14 −3
Original line number Original line Diff line number Diff line
@@ -169,10 +169,21 @@ static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable) 
	if (rc)

	if (rc)

		return rc;

		return rc;





	if (amdgpu_in_reset(adev)) {

		irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;

		irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;



		/* During gpu-reset we disable and then enable vblank irq, so

		 * don't use amdgpu_irq_get/put() to avoid refcount change.

		 */

		if (!dc_interrupt_set(adev->dm.dc, irq_source, enable))

		if (!dc_interrupt_set(adev->dm.dc, irq_source, enable))

		return -EBUSY;

			rc = -EBUSY;

	} else {

		rc = (enable)

			? amdgpu_irq_get(adev, &adev->crtc_irq, acrtc->crtc_id)

			: amdgpu_irq_put(adev, &adev->crtc_irq, acrtc->crtc_id);

	}



	if (rc)

		return rc;





skip:

skip:

	if (amdgpu_in_reset(adev))

	if (amdgpu_in_reset(adev))

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c

+20 −0
Original line number Original line Diff line number Diff line
@@ -1697,6 +1697,23 @@ static void dcn314_get_panel_config_defaults(struct dc_panel_config *panel_confi 
	*panel_config = panel_config_defaults;

	*panel_config = panel_config_defaults;

}

}





static bool filter_modes_for_single_channel_workaround(struct dc *dc,

		struct dc_state *context)

{

	// Filter 2K@240Hz+8K@24fps above combination timing if memory only has single dimm LPDDR

	if (dc->clk_mgr->bw_params->vram_type == 34 && dc->clk_mgr->bw_params->num_channels < 2) {

		int total_phy_pix_clk = 0;



		for (int i = 0; i < context->stream_count; i++)

			if (context->res_ctx.pipe_ctx[i].stream)

				total_phy_pix_clk += context->res_ctx.pipe_ctx[i].stream->phy_pix_clk;



		if (total_phy_pix_clk >= (1148928+826260)) //2K@240Hz+8K@24fps

			return true;

	}

	return false;

}



bool dcn314_validate_bandwidth(struct dc *dc,

bool dcn314_validate_bandwidth(struct dc *dc,

		struct dc_state *context,

		struct dc_state *context,

		bool fast_validate)

		bool fast_validate)
@@ -1712,6 +1729,9 @@ bool dcn314_validate_bandwidth(struct dc *dc, 




	BW_VAL_TRACE_COUNT();

	BW_VAL_TRACE_COUNT();





	if (filter_modes_for_single_channel_workaround(dc, context))

		goto validate_fail;



	DC_FP_START();

	DC_FP_START();

	// do not support self refresh only

	// do not support self refresh only

	out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, false);

	out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, false);

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -222,7 +222,7 @@ struct _vcs_dpi_ip_params_st dcn3_15_ip = { 
	.maximum_dsc_bits_per_component = 10,

	.maximum_dsc_bits_per_component = 10,

	.dsc422_native_support = false,

	.dsc422_native_support = false,

	.is_line_buffer_bpp_fixed = true,

	.is_line_buffer_bpp_fixed = true,

	.line_buffer_fixed_bpp = 49,

	.line_buffer_fixed_bpp = 48,

	.line_buffer_size_bits = 789504,

	.line_buffer_size_bits = 789504,

	.max_line_buffer_lines = 12,

	.max_line_buffer_lines = 12,

	.writeback_interface_buffer_size_kbytes = 90,

	.writeback_interface_buffer_size_kbytes = 90,

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

+4 −0
Original line number Original line Diff line number Diff line
@@ -934,6 +934,10 @@ bool psr_su_set_dsc_slice_height(struct dc *dc, struct dc_link *link, 




	pic_height = stream->timing.v_addressable +

	pic_height = stream->timing.v_addressable +

		stream->timing.v_border_top + stream->timing.v_border_bottom;

		stream->timing.v_border_top + stream->timing.v_border_bottom;



	if (stream->timing.dsc_cfg.num_slices_v == 0)

		return false;



	slice_height = pic_height / stream->timing.dsc_cfg.num_slices_v;

	slice_height = pic_height / stream->timing.dsc_cfg.num_slices_v;

	config->dsc_slice_height = slice_height;

	config->dsc_slice_height = slice_height;