Commit 2af39b99 authored by Paolo Abeni's avatar Paolo Abeni
Browse files

Merge branch 'rk3588-ethernet-support' 

Sebastian Reichel says:

====================
RK3588 Ethernet Support

This adds ethernet support for the RK3588(s) SoCs.

Changes since PATCHv2:
 * Rebased to v6.0-rc1
 * Wrap DT bindings additions at 80 characters
 * Add Acked-by from Krzysztof

Changes since PATCHv1:
 * Drop first patch (not required) and rebase second patch accordingly
 * Rename DT property rockchip,php_grf -> rockchip,php-grf
====================

Link: https://lore.kernel.org/r/20220830154559.61506-1-sebastian.reichel@collabora.com


Signed-off-by: default avatarPaolo Abeni <pabeni@redhat.com>
parents 99c969a8 a2b77831

Documentation/devicetree/bindings/net/rockchip-dwmac.yaml

+7 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ select: 
          - rockchip,rk3368-gmac

          - rockchip,rk3399-gmac

          - rockchip,rk3568-gmac

          - rockchip,rk3588-gmac

          - rockchip,rv1108-gmac

  required:

    - compatible
@@ -50,6 +51,7 @@ properties: 
      - items:

          - enum:

              - rockchip,rk3568-gmac

              - rockchip,rk3588-gmac

          - const: snps,dwmac-4.20a



  clocks:
@@ -81,6 +83,11 @@ properties: 
    description: The phandle of the syscon node for the general register file.

    $ref: /schemas/types.yaml#/definitions/phandle



  rockchip,php-grf:

    description:

      The phandle of the syscon node for the peripheral general register file.

    $ref: /schemas/types.yaml#/definitions/phandle



  tx_delay:

    description: Delay value for TXD timing. Range value is 0~0x7F, 0x30 as default.

    $ref: /schemas/types.yaml#/definitions/uint32

Documentation/devicetree/bindings/net/snps,dwmac.yaml

+1 −0
Original line number Diff line number Diff line
@@ -74,6 +74,7 @@ properties: 
        - rockchip,rk3328-gmac

        - rockchip,rk3366-gmac

        - rockchip,rk3368-gmac

        - rockchip,rk3588-gmac

        - rockchip,rk3399-gmac

        - rockchip,rv1108-gmac

        - snps,dwmac

drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c

+155 −0
Original line number Diff line number Diff line
@@ -32,6 +32,8 @@ struct rk_gmac_ops { 
	void (*set_to_rmii)(struct rk_priv_data *bsp_priv);

	void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);

	void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);

	void (*set_clock_selection)(struct rk_priv_data *bsp_priv, bool input,

				    bool enable);

	void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv);

	bool regs_valid;

	u32 regs[];
@@ -66,6 +68,7 @@ struct rk_priv_data { 
	int rx_delay;



	struct regmap *grf;

	struct regmap *php_grf;

};



#define HIWORD_UPDATE(val, mask, shift) \
@@ -1101,6 +1104,147 @@ static const struct rk_gmac_ops rk3568_ops = { 
	},

};



/* sys_grf */

#define RK3588_GRF_GMAC_CON7			0X031c

#define RK3588_GRF_GMAC_CON8			0X0320

#define RK3588_GRF_GMAC_CON9			0X0324



#define RK3588_GMAC_RXCLK_DLY_ENABLE(id)	GRF_BIT(2 * (id) + 3)

#define RK3588_GMAC_RXCLK_DLY_DISABLE(id)	GRF_CLR_BIT(2 * (id) + 3)

#define RK3588_GMAC_TXCLK_DLY_ENABLE(id)	GRF_BIT(2 * (id) + 2)

#define RK3588_GMAC_TXCLK_DLY_DISABLE(id)	GRF_CLR_BIT(2 * (id) + 2)



#define RK3588_GMAC_CLK_RX_DL_CFG(val)		HIWORD_UPDATE(val, 0xFF, 8)

#define RK3588_GMAC_CLK_TX_DL_CFG(val)		HIWORD_UPDATE(val, 0xFF, 0)



/* php_grf */

#define RK3588_GRF_GMAC_CON0			0X0008

#define RK3588_GRF_CLK_CON1			0X0070



#define RK3588_GMAC_PHY_INTF_SEL_RGMII(id)	\

	(GRF_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_CLR_BIT(5 + (id) * 6))

#define RK3588_GMAC_PHY_INTF_SEL_RMII(id)	\

	(GRF_CLR_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_BIT(5 + (id) * 6))



#define RK3588_GMAC_CLK_RMII_MODE(id)		GRF_BIT(5 * (id))

#define RK3588_GMAC_CLK_RGMII_MODE(id)		GRF_CLR_BIT(5 * (id))



#define RK3588_GMAC_CLK_SELET_CRU(id)		GRF_BIT(5 * (id) + 4)

#define RK3588_GMAC_CLK_SELET_IO(id)		GRF_CLR_BIT(5 * (id) + 4)



#define RK3588_GMA_CLK_RMII_DIV2(id)		GRF_BIT(5 * (id) + 2)

#define RK3588_GMA_CLK_RMII_DIV20(id)		GRF_CLR_BIT(5 * (id) + 2)



#define RK3588_GMAC_CLK_RGMII_DIV1(id)		\

			(GRF_CLR_BIT(5 * (id) + 2) | GRF_CLR_BIT(5 * (id) + 3))

#define RK3588_GMAC_CLK_RGMII_DIV5(id)		\

			(GRF_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3))

#define RK3588_GMAC_CLK_RGMII_DIV50(id)		\

			(GRF_CLR_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3))



#define RK3588_GMAC_CLK_RMII_GATE(id)		GRF_BIT(5 * (id) + 1)

#define RK3588_GMAC_CLK_RMII_NOGATE(id)		GRF_CLR_BIT(5 * (id) + 1)



static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv,

				int tx_delay, int rx_delay)

{

	struct device *dev = &bsp_priv->pdev->dev;

	u32 offset_con, id = bsp_priv->id;



	if (IS_ERR(bsp_priv->grf) || IS_ERR(bsp_priv->php_grf)) {

		dev_err(dev, "Missing rockchip,grf or rockchip,php_grf property\n");

		return;

	}



	offset_con = bsp_priv->id == 1 ? RK3588_GRF_GMAC_CON9 :

					 RK3588_GRF_GMAC_CON8;



	regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0,

		     RK3588_GMAC_PHY_INTF_SEL_RGMII(id));



	regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1,

		     RK3588_GMAC_CLK_RGMII_MODE(id));



	regmap_write(bsp_priv->grf, RK3588_GRF_GMAC_CON7,

		     RK3588_GMAC_RXCLK_DLY_ENABLE(id) |

		     RK3588_GMAC_TXCLK_DLY_ENABLE(id));



	regmap_write(bsp_priv->grf, offset_con,

		     RK3588_GMAC_CLK_RX_DL_CFG(rx_delay) |

		     RK3588_GMAC_CLK_TX_DL_CFG(tx_delay));

}



static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv)

{

	struct device *dev = &bsp_priv->pdev->dev;



	if (IS_ERR(bsp_priv->php_grf)) {

		dev_err(dev, "%s: Missing rockchip,php_grf property\n", __func__);

		return;

	}



	regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0,

		     RK3588_GMAC_PHY_INTF_SEL_RMII(bsp_priv->id));



	regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1,

		     RK3588_GMAC_CLK_RMII_MODE(bsp_priv->id));

}



static void rk3588_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed)

{

	struct device *dev = &bsp_priv->pdev->dev;

	unsigned int val = 0, id = bsp_priv->id;



	switch (speed) {

	case 10:

		if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)

			val = RK3588_GMA_CLK_RMII_DIV20(id);

		else

			val = RK3588_GMAC_CLK_RGMII_DIV50(id);

		break;

	case 100:

		if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)

			val = RK3588_GMA_CLK_RMII_DIV2(id);

		else

			val = RK3588_GMAC_CLK_RGMII_DIV5(id);

		break;

	case 1000:

		if (bsp_priv->phy_iface != PHY_INTERFACE_MODE_RMII)

			val = RK3588_GMAC_CLK_RGMII_DIV1(id);

		else

			goto err;

		break;

	default:

		goto err;

	}



	regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val);



	return;

err:

	dev_err(dev, "unknown speed value for GMAC speed=%d", speed);

}



static void rk3588_set_clock_selection(struct rk_priv_data *bsp_priv, bool input,

				       bool enable)

{

	unsigned int val = input ? RK3588_GMAC_CLK_SELET_IO(bsp_priv->id) :

				   RK3588_GMAC_CLK_SELET_CRU(bsp_priv->id);



	val |= enable ? RK3588_GMAC_CLK_RMII_NOGATE(bsp_priv->id) :

			RK3588_GMAC_CLK_RMII_GATE(bsp_priv->id);



	regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val);

}



static const struct rk_gmac_ops rk3588_ops = {

	.set_to_rgmii = rk3588_set_to_rgmii,

	.set_to_rmii = rk3588_set_to_rmii,

	.set_rgmii_speed = rk3588_set_gmac_speed,

	.set_rmii_speed = rk3588_set_gmac_speed,

	.set_clock_selection = rk3588_set_clock_selection,

};



#define RV1108_GRF_GMAC_CON0		0X0900



/* RV1108_GRF_GMAC_CON0 */
@@ -1304,6 +1448,10 @@ static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable) 
			if (!IS_ERR(bsp_priv->clk_mac_speed))

				clk_prepare_enable(bsp_priv->clk_mac_speed);



			if (bsp_priv->ops && bsp_priv->ops->set_clock_selection)

				bsp_priv->ops->set_clock_selection(bsp_priv,

					       bsp_priv->clock_input, true);



			/**

			 * if (!IS_ERR(bsp_priv->clk_mac))

			 *	clk_prepare_enable(bsp_priv->clk_mac);
@@ -1330,6 +1478,10 @@ static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable) 
			clk_disable_unprepare(bsp_priv->mac_clk_tx);



			clk_disable_unprepare(bsp_priv->clk_mac_speed);



			if (bsp_priv->ops && bsp_priv->ops->set_clock_selection)

				bsp_priv->ops->set_clock_selection(bsp_priv,

					      bsp_priv->clock_input, false);

			/**

			 * if (!IS_ERR(bsp_priv->clk_mac))

			 *	clk_disable_unprepare(bsp_priv->clk_mac);
@@ -1444,6 +1596,8 @@ static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev, 


	bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,

							"rockchip,grf");

	bsp_priv->php_grf = syscon_regmap_lookup_by_phandle(dev->of_node,

							    "rockchip,php-grf");



	if (plat->phy_node) {

		bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node,
@@ -1680,6 +1834,7 @@ static const struct of_device_id rk_gmac_dwmac_match[] = { 
	{ .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },

	{ .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },

	{ .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops },

	{ .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops },

	{ .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops },

	{ }

};