Commit 2aaf69dc authored by Sheng Yang's avatar Sheng Yang Committed by Avi Kivity
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KVM: MMU: Map device MMIO as UC in EPT 



Software are not allow to access device MMIO using cacheable memory type, the
patch limit MMIO region with UC and WC(guest can select WC using PAT and
PCD/PWT).

Signed-off-by: default avatarSheng Yang <sheng@linux.intel.com>
Signed-off-by: default avatarAvi Kivity <avi@redhat.com>
parent abe6655d

arch/x86/kvm/mmu.c

+7 −2
Original line number Diff line number Diff line
@@ -1698,8 +1698,13 @@ static int set_spte(struct kvm_vcpu *vcpu, u64 *shadow_pte, 
	if (largepage)

		spte |= PT_PAGE_SIZE_MASK;

	if (mt_mask) {

		if (!kvm_is_mmio_pfn(pfn)) {

			mt_mask = get_memory_type(vcpu, gfn) <<

				kvm_x86_ops->get_mt_mask_shift();

			mt_mask |= VMX_EPT_IGMT_BIT;

		} else

			mt_mask = MTRR_TYPE_UNCACHABLE <<

				kvm_x86_ops->get_mt_mask_shift();

		spte |= mt_mask;

	}

arch/x86/kvm/vmx.c

+1 −2
Original line number Diff line number Diff line
@@ -3687,8 +3687,7 @@ static int __init vmx_init(void) 
	if (vm_need_ept()) {

		bypass_guest_pf = 0;

		kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |

			VMX_EPT_WRITABLE_MASK |

			VMX_EPT_IGMT_BIT);

			VMX_EPT_WRITABLE_MASK);

		kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,

				VMX_EPT_EXECUTABLE_MASK,

				VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT);