Commit 2aae5eaa authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Bjorn Andersson
Browse files

dt-bindings: clock: Add SM8350 VIDEOCC 



SM8350, like most recent higher-end chips has a separate clock
controller block just for the Venus IP. Document it.

The binding was separated as the driver, unlike the earlier ones, doesn't
expect clock-names to keep it easier to maintain.

Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230413-topic-lahaina_vidcc-v4-1-86c714a66a81@linaro.org
parent ac9a7868

Documentation/devicetree/bindings/clock/qcom,sm8350-videocc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,sm8350-videocc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm SM8350 Video Clock & Reset Controller



maintainers:

  - Konrad Dybcio <konrad.dybcio@linaro.org>



description: |

  Qualcomm video clock control module provides the clocks, resets and power

  domains on Qualcomm SoCs.



  See also::

    include/dt-bindings/clock/qcom,videocc-sm8350.h

    include/dt-bindings/reset/qcom,videocc-sm8350.h



properties:

  compatible:

    const: qcom,sm8350-videocc



  clocks:

    items:

      - description: Board XO source

      - description: Board active XO source

      - description: Board sleep clock



  power-domains:

    description:

      A phandle and PM domain specifier for the MMCX power domain.

    maxItems: 1



  required-opps:

    description:

      A phandle to an OPP node describing required MMCX performance point.

    maxItems: 1



required:

  - compatible

  - clocks

  - power-domains

  - required-opps



allOf:

  - $ref: qcom,gcc.yaml#



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,rpmh.h>

    #include <dt-bindings/power/qcom-rpmpd.h>



    clock-controller@abf0000 {

      compatible = "qcom,sm8350-videocc";

      reg = <0x0abf0000 0x10000>;

      clocks = <&rpmhcc RPMH_CXO_CLK>,

               <&rpmhcc RPMH_CXO_CLK_A>,

               <&sleep_clk>;

      power-domains = <&rpmhpd SM8350_MMCX>;

      required-opps = <&rpmhpd_opp_low_svs>;

      #clock-cells = <1>;

      #reset-cells = <1>;

      #power-domain-cells = <1>;

    };

...

include/dt-bindings/clock/qcom,sm8350-videocc.h

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */

/*

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2023, Linaro Limited

 */



#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8350_H

#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8350_H



/* Clocks */

#define VIDEO_CC_AHB_CLK_SRC					0

#define VIDEO_CC_MVS0_CLK					1

#define VIDEO_CC_MVS0_CLK_SRC					2

#define VIDEO_CC_MVS0_DIV_CLK_SRC				3

#define VIDEO_CC_MVS0C_CLK					4

#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC				5

#define VIDEO_CC_MVS1_CLK					6

#define VIDEO_CC_MVS1_CLK_SRC					7

#define VIDEO_CC_MVS1_DIV2_CLK					8

#define VIDEO_CC_MVS1_DIV_CLK_SRC				9

#define VIDEO_CC_MVS1C_CLK					10

#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC				11

#define VIDEO_CC_SLEEP_CLK					12

#define VIDEO_CC_SLEEP_CLK_SRC					13

#define VIDEO_CC_XO_CLK_SRC					14

#define VIDEO_PLL0						15

#define VIDEO_PLL1						16



/* GDSCs */

#define MVS0C_GDSC						0

#define MVS1C_GDSC						1

#define MVS0_GDSC						2

#define MVS1_GDSC						3



#endif

include/dt-bindings/reset/qcom,sm8350-videocc.h

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */

/*

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2023, Linaro Limited

 */



#ifndef _DT_BINDINGS_RESET_QCOM_VIDEO_CC_SM8350_H

#define _DT_BINDINGS_RESET_QCOM_VIDEO_CC_SM8350_H



#define VIDEO_CC_CVP_INTERFACE_BCR				0

#define VIDEO_CC_CVP_MVS0_BCR					1

#define VIDEO_CC_MVS0C_CLK_ARES					2

#define VIDEO_CC_CVP_MVS0C_BCR					3

#define VIDEO_CC_CVP_MVS1_BCR					4

#define VIDEO_CC_MVS1C_CLK_ARES					5

#define VIDEO_CC_CVP_MVS1C_BCR					6



#endif