Commit 2a9aa52e authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amd/pm: fulfill the OD support for SMU13.0.7 



Fulfill the interfaces for OD settings retrieving and setting.

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1718e973

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

+402 −43
Original line number Diff line number Diff line
@@ -1022,16 +1022,118 @@ static int smu_v13_0_7_get_current_clk_freq_by_table(struct smu_context *smu, 
						value);

}



static bool smu_v13_0_7_is_od_feature_supported(struct smu_context *smu,

						int od_feature_bit)

{

	PPTable_t *pptable = smu->smu_table.driver_pptable;

	const OverDriveLimits_t * const overdrive_upperlimits =

				&pptable->SkuTable.OverDriveLimitsBasicMax;



	return overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit);

}



static void smu_v13_0_7_get_od_setting_limits(struct smu_context *smu,

					      int od_feature_bit,

					      bool lower_boundary,

					      int32_t *min,

					      int32_t *max)

{

	PPTable_t *pptable = smu->smu_table.driver_pptable;

	const OverDriveLimits_t * const overdrive_upperlimits =

				&pptable->SkuTable.OverDriveLimitsBasicMax;

	const OverDriveLimits_t * const overdrive_lowerlimits =

				&pptable->SkuTable.OverDriveLimitsMin;

	int32_t od_min_setting, od_max_setting;



	switch (od_feature_bit) {

	case PP_OD_FEATURE_GFXCLK_BIT:

		if (lower_boundary) {

			od_min_setting = overdrive_lowerlimits->GfxclkFmin;

			od_max_setting = overdrive_upperlimits->GfxclkFmin;

		} else {

			od_min_setting = overdrive_lowerlimits->GfxclkFmax;

			od_max_setting = overdrive_upperlimits->GfxclkFmax;

		}

		break;

	case PP_OD_FEATURE_UCLK_BIT:

		if (lower_boundary) {

			od_min_setting = overdrive_lowerlimits->UclkFmin;

			od_max_setting = overdrive_upperlimits->UclkFmin;

		} else {

			od_min_setting = overdrive_lowerlimits->UclkFmax;

			od_max_setting = overdrive_upperlimits->UclkFmax;

		}

		break;

	case PP_OD_FEATURE_GFX_VF_CURVE_BIT:

		od_min_setting = overdrive_lowerlimits->VoltageOffsetPerZoneBoundary;

		od_max_setting = overdrive_upperlimits->VoltageOffsetPerZoneBoundary;

		break;

	default:

		break;

	}



	if (min)

		*min = od_min_setting;

	if (max)

		*max = od_max_setting;

}



static void smu_v13_0_7_dump_od_table(struct smu_context *smu,

				      OverDriveTableExternal_t *od_table)

{

	struct amdgpu_device *adev = smu->adev;



	dev_dbg(adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->OverDriveTable.GfxclkFmin,

						     od_table->OverDriveTable.GfxclkFmax);

	dev_dbg(adev->dev, "OD: Uclk: (%d, %d)\n", od_table->OverDriveTable.UclkFmin,

						   od_table->OverDriveTable.UclkFmax);

}



static int smu_v13_0_7_get_overdrive_table(struct smu_context *smu,

					   OverDriveTableExternal_t *od_table)

{

	int ret = 0;



	ret = smu_cmn_update_table(smu,

				   SMU_TABLE_OVERDRIVE,

				   0,

				   (void *)od_table,

				   false);

	if (ret)

		dev_err(smu->adev->dev, "Failed to get overdrive table!\n");



	return ret;

}



static int smu_v13_0_7_upload_overdrive_table(struct smu_context *smu,

					      OverDriveTableExternal_t *od_table)

{

	int ret = 0;



	ret = smu_cmn_update_table(smu,

				   SMU_TABLE_OVERDRIVE,

				   0,

				   (void *)od_table,

				   true);

	if (ret)

		dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");



	return ret;

}



static int smu_v13_0_7_print_clk_levels(struct smu_context *smu,

					enum smu_clk_type clk_type,

					char *buf)

{

	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;

	struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;

	OverDriveTableExternal_t *od_table =

		(OverDriveTableExternal_t *)smu->smu_table.overdrive_table;

	struct smu_13_0_dpm_table *single_dpm_table;

	struct smu_13_0_pcie_table *pcie_table;

	uint32_t gen_speed, lane_width;

	int i, curr_freq, size = 0;

	int32_t min_value, max_value;

	int ret = 0;



	smu_cmn_get_sysfs_buf(&buf, &size);
@@ -1148,6 +1250,89 @@ static int smu_v13_0_7_print_clk_levels(struct smu_context *smu, 
					"*" : "");

		break;



	case SMU_OD_SCLK:

		if (!smu_v13_0_7_is_od_feature_supported(smu,

							 PP_OD_FEATURE_GFXCLK_BIT))

			break;



		size += sysfs_emit_at(buf, size, "OD_SCLK:\n");

		size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n",

					od_table->OverDriveTable.GfxclkFmin,

					od_table->OverDriveTable.GfxclkFmax);

		break;



	case SMU_OD_MCLK:

		if (!smu_v13_0_7_is_od_feature_supported(smu,

							 PP_OD_FEATURE_UCLK_BIT))

			break;



		size += sysfs_emit_at(buf, size, "OD_MCLK:\n");

		size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n",

					od_table->OverDriveTable.UclkFmin,

					od_table->OverDriveTable.UclkFmax);

		break;



	case SMU_OD_VDDC_CURVE:

		if (!smu_v13_0_7_is_od_feature_supported(smu,

							 PP_OD_FEATURE_GFX_VF_CURVE_BIT))

			break;



		size += sysfs_emit_at(buf, size, "OD_VDDC_CURVE:\n");

		for (i = 0; i < PP_NUM_OD_VF_CURVE_POINTS; i++)

			size += sysfs_emit_at(buf, size, "%d: %dmv\n",

						i,

						od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[i]);

		break;



	case SMU_OD_RANGE:

		if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT) &&

		    !smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT) &&

		    !smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT))

			break;



		size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");



		if (smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) {

			smu_v13_0_7_get_od_setting_limits(smu,

							  PP_OD_FEATURE_GFXCLK_BIT,

							  true,

							  &min_value,

							  NULL);

			smu_v13_0_7_get_od_setting_limits(smu,

							  PP_OD_FEATURE_GFXCLK_BIT,

							  false,

							  NULL,

							  &max_value);

			size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",

					      min_value, max_value);

		}



		if (smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT)) {

			smu_v13_0_7_get_od_setting_limits(smu,

							  PP_OD_FEATURE_UCLK_BIT,

							  true,

							  &min_value,

							  NULL);

			smu_v13_0_7_get_od_setting_limits(smu,

							  PP_OD_FEATURE_UCLK_BIT,

							  false,

							  NULL,

							  &max_value);

			size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",

					      min_value, max_value);

		}



		if (smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) {

			smu_v13_0_7_get_od_setting_limits(smu,

							  PP_OD_FEATURE_GFX_VF_CURVE_BIT,

							  true,

							  &min_value,

							  &max_value);

			size += sysfs_emit_at(buf, size, "VDDC_CURVE: %7dmv %10dmv\n",

					      min_value, max_value);

		}

		break;



	default:

		break;

	}
@@ -1155,6 +1340,222 @@ static int smu_v13_0_7_print_clk_levels(struct smu_context *smu, 
	return size;

}



static int smu_v13_0_7_od_edit_dpm_table(struct smu_context *smu,

					 enum PP_OD_DPM_TABLE_COMMAND type,

					 long input[],

					 uint32_t size)

{

	struct smu_table_context *table_context = &smu->smu_table;

	OverDriveTableExternal_t *od_table =

		(OverDriveTableExternal_t *)table_context->overdrive_table;

	struct amdgpu_device *adev = smu->adev;

	uint32_t offset_of_featurectrlmask;

	int32_t minimum, maximum;

	uint32_t feature_ctrlmask;

	int i, ret = 0;



	switch (type) {

	case PP_OD_EDIT_SCLK_VDDC_TABLE:

		if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) {

			dev_warn(adev->dev, "GFXCLK_LIMITS setting not supported!\n");

			return -ENOTSUPP;

		}



		for (i = 0; i < size; i += 2) {

			if (i + 2 > size) {

				dev_info(adev->dev, "invalid number of input parameters %d\n", size);

				return -EINVAL;

			}



			switch (input[i]) {

			case 0:

				smu_v13_0_7_get_od_setting_limits(smu,

								  PP_OD_FEATURE_GFXCLK_BIT,

								  true,

								  &minimum,

								  &maximum);

				if (input[i + 1] < minimum ||

				    input[i + 1] > maximum) {

					dev_info(adev->dev, "GfxclkFmin (%ld) must be within [%u, %u]!\n",

						input[i + 1], minimum, maximum);

					return -EINVAL;

				}



				od_table->OverDriveTable.GfxclkFmin = input[i + 1];

				od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_GFXCLK_BIT;

				break;



			case 1:

				smu_v13_0_7_get_od_setting_limits(smu,

								  PP_OD_FEATURE_GFXCLK_BIT,

								  false,

								  &minimum,

								  &maximum);

				if (input[i + 1] < minimum ||

				    input[i + 1] > maximum) {

					dev_info(adev->dev, "GfxclkFmax (%ld) must be within [%u, %u]!\n",

						input[i + 1], minimum, maximum);

					return -EINVAL;

				}



				od_table->OverDriveTable.GfxclkFmax = input[i + 1];

				od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_GFXCLK_BIT;

				break;



			default:

				dev_info(adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);

				dev_info(adev->dev, "Supported indices: [0:min,1:max]\n");

				return -EINVAL;

			}

		}



		if (od_table->OverDriveTable.GfxclkFmin > od_table->OverDriveTable.GfxclkFmax) {

			dev_err(adev->dev,

				"Invalid setting: GfxclkFmin(%u) is bigger than GfxclkFmax(%u)\n",

				(uint32_t)od_table->OverDriveTable.GfxclkFmin,

				(uint32_t)od_table->OverDriveTable.GfxclkFmax);

			return -EINVAL;

		}

		break;



	case PP_OD_EDIT_MCLK_VDDC_TABLE:

		if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT)) {

			dev_warn(adev->dev, "UCLK_LIMITS setting not supported!\n");

			return -ENOTSUPP;

		}



		for (i = 0; i < size; i += 2) {

			if (i + 2 > size) {

				dev_info(adev->dev, "invalid number of input parameters %d\n", size);

				return -EINVAL;

			}



			switch (input[i]) {

			case 0:

				smu_v13_0_7_get_od_setting_limits(smu,

								  PP_OD_FEATURE_UCLK_BIT,

								  true,

								  &minimum,

								  &maximum);

				if (input[i + 1] < minimum ||

				    input[i + 1] > maximum) {

					dev_info(adev->dev, "UclkFmin (%ld) must be within [%u, %u]!\n",

						input[i + 1], minimum, maximum);

					return -EINVAL;

				}



				od_table->OverDriveTable.UclkFmin = input[i + 1];

				od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_UCLK_BIT;

				break;



			case 1:

				smu_v13_0_7_get_od_setting_limits(smu,

								  PP_OD_FEATURE_UCLK_BIT,

								  false,

								  &minimum,

								  &maximum);

				if (input[i + 1] < minimum ||

				    input[i + 1] > maximum) {

					dev_info(adev->dev, "UclkFmax (%ld) must be within [%u, %u]!\n",

						input[i + 1], minimum, maximum);

					return -EINVAL;

				}



				od_table->OverDriveTable.UclkFmax = input[i + 1];

				od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_UCLK_BIT;

				break;



			default:

				dev_info(adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);

				dev_info(adev->dev, "Supported indices: [0:min,1:max]\n");

				return -EINVAL;

			}

		}



		if (od_table->OverDriveTable.UclkFmin > od_table->OverDriveTable.UclkFmax) {

			dev_err(adev->dev,

				"Invalid setting: UclkFmin(%u) is bigger than UclkFmax(%u)\n",

				(uint32_t)od_table->OverDriveTable.UclkFmin,

				(uint32_t)od_table->OverDriveTable.UclkFmax);

			return -EINVAL;

		}

		break;



	case PP_OD_EDIT_VDDC_CURVE:

		if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) {

			dev_warn(adev->dev, "VF curve setting not supported!\n");

			return -ENOTSUPP;

		}



		if (input[0] >= PP_NUM_OD_VF_CURVE_POINTS ||

		    input[0] < 0)

			return -EINVAL;



		smu_v13_0_7_get_od_setting_limits(smu,

						  PP_OD_FEATURE_GFX_VF_CURVE_BIT,

						  true,

						  &minimum,

						  &maximum);

		if (input[1] < minimum ||

		    input[1] > maximum) {

			dev_info(adev->dev, "Voltage offset (%ld) must be within [%d, %d]!\n",

				 input[1], minimum, maximum);

			return -EINVAL;

		}



		od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[input[0]] = input[1];

		od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_GFX_VF_CURVE_BIT;

		break;



	case PP_OD_RESTORE_DEFAULT_TABLE:

		feature_ctrlmask = od_table->OverDriveTable.FeatureCtrlMask;

		memcpy(od_table,

		       table_context->boot_overdrive_table,

		       sizeof(OverDriveTableExternal_t));

		od_table->OverDriveTable.FeatureCtrlMask = feature_ctrlmask;

		fallthrough;



	case PP_OD_COMMIT_DPM_TABLE:

		/*

		 * The member below instructs PMFW the settings focused in

		 * this single operation.

		 * `uint32_t FeatureCtrlMask;`

		 * It does not contain actual informations about user's custom

		 * settings. Thus we do not cache it.

		 */

		offset_of_featurectrlmask = offsetof(OverDriveTable_t, FeatureCtrlMask);

		if (memcmp(od_table + offset_of_featurectrlmask,

			   table_context->user_overdrive_table + offset_of_featurectrlmask,

			   sizeof(OverDriveTableExternal_t) - offset_of_featurectrlmask)) {

			smu_v13_0_7_dump_od_table(smu, od_table);



			ret = smu_v13_0_7_upload_overdrive_table(smu, od_table);

			if (ret) {

				dev_err(adev->dev, "Failed to upload overdrive table!\n");

				return ret;

			}



			od_table->OverDriveTable.FeatureCtrlMask = 0;

			memcpy(table_context->user_overdrive_table + offset_of_featurectrlmask,

			       od_table + offset_of_featurectrlmask,

			       sizeof(OverDriveTableExternal_t) - offset_of_featurectrlmask);



			if (!memcmp(table_context->user_overdrive_table,

				    table_context->boot_overdrive_table,

				    sizeof(OverDriveTableExternal_t)))

				smu->user_dpm_profile.user_od = false;

			else

				smu->user_dpm_profile.user_od = true;

		}

		break;



	default:

		return -ENOSYS;

	}



	return ret;

}



static int smu_v13_0_7_force_clk_levels(struct smu_context *smu,

					enum smu_clk_type clk_type,

					uint32_t mask)
@@ -1380,49 +1781,6 @@ static ssize_t smu_v13_0_7_get_gpu_metrics(struct smu_context *smu, 
	return sizeof(struct gpu_metrics_v1_3);

}



static int smu_v13_0_7_get_overdrive_table(struct smu_context *smu,

					   OverDriveTableExternal_t *od_table)

{

	int ret = 0;



	ret = smu_cmn_update_table(smu,

				   SMU_TABLE_OVERDRIVE,

				   0,

				   (void *)od_table,

				   false);

	if (ret)

		dev_err(smu->adev->dev, "Failed to get overdrive table!\n");



	return ret;

}



static int smu_v13_0_7_upload_overdrive_table(struct smu_context *smu,

					      OverDriveTableExternal_t *od_table)

{

	int ret = 0;



	ret = smu_cmn_update_table(smu,

				   SMU_TABLE_OVERDRIVE,

				   0,

				   (void *)od_table,

				   true);

	if (ret)

		dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");



	return ret;

}



static void smu_v13_0_7_dump_od_table(struct smu_context *smu,

				      OverDriveTableExternal_t *od_table)

{

	struct amdgpu_device *adev = smu->adev;



	dev_dbg(adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->OverDriveTable.GfxclkFmin,

						     od_table->OverDriveTable.GfxclkFmax);

	dev_dbg(adev->dev, "OD: Uclk: (%d, %d)\n", od_table->OverDriveTable.UclkFmin,

						   od_table->OverDriveTable.UclkFmax);

}



static int smu_v13_0_7_set_default_od_settings(struct smu_context *smu)

{

	OverDriveTableExternal_t *od_table =
@@ -1886,6 +2244,7 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = { 
	.set_soft_freq_limited_range = smu_v13_0_set_soft_freq_limited_range,

	.set_default_od_settings = smu_v13_0_7_set_default_od_settings,

	.restore_user_od_settings = smu_v13_0_7_restore_user_od_settings,

	.od_edit_dpm_table = smu_v13_0_7_od_edit_dpm_table,

	.set_performance_level = smu_v13_0_set_performance_level,

	.gfx_off_control = smu_v13_0_gfx_off_control,

	.get_fan_speed_pwm = smu_v13_0_7_get_fan_speed_pwm,