Commit 2a7005c8 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-gt-next-2021-06-10' of... 

Merge tag 'drm-intel-gt-next-2021-06-10' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-next

UAPI Changes:

- Disable mmap ioctl for gen12+ (excl. TGL-LP)
- Start enabling HuC loading by default for upcoming Gen12+
  platforms (excludes TGL and RKL)

Core Changes:

- Backmerge of drm-next

Driver Changes:

- Revert "i915: use io_mapping_map_user" (Eero, Matt A)
- Initialize the TTM device and memory managers (Thomas)
- Major rework to the GuC submission backend to prepare
  for enabling on new platforms (Michal Wa., Daniele,
  Matt B, Rodrigo)
- Fix i915_sg_page_sizes to record dma segments rather
  than physical pages (Thomas)

- Locking rework to prep for TTM conversion (Thomas)
- Replace IS_GEN and friends with GRAPHICS_VER (Lucas)
- Use DEVICE_ATTR_RO macro (Yue)
- Static code checker fixes (Zhihao)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/YMHeDxg9VLiFtyn3@jlahtine-mobl.ger.corp.intel.com
parents 0666cba1 47c65b38

drivers/gpu/drm/i915/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -20,13 +20,13 @@ config DRM_I915 
	select INPUT if ACPI

	select ACPI_VIDEO if ACPI

	select ACPI_BUTTON if ACPI

	select IO_MAPPING

	select SYNC_FILE

	select IOSF_MBI

	select CRC32

	select SND_HDA_I915 if SND_HDA_CORE

	select CEC_CORE if CEC_NOTIFIER

	select VMAP_PFN

	select DRM_TTM

	help

	  Choose this option if you have a system that has "Intel Graphics

	  Media Accelerator" or "HD Graphics" integrated graphics,

drivers/gpu/drm/i915/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -50,6 +50,7 @@ i915-y += i915_drv.o \ 
	  intel_memory_region.o \

	  intel_pch.o \

	  intel_pm.o \

	  intel_region_ttm.o \

	  intel_runtime_pm.o \

	  intel_sideband.o \

	  intel_step.o \
@@ -160,7 +161,6 @@ gem-y += \ 
i915-y += \

	  $(gem-y) \

	  i915_active.o \

	  i915_buddy.o \

	  i915_cmd_parser.o \

	  i915_gem_evict.o \

	  i915_gem_gtt.o \

drivers/gpu/drm/i915/gem/i915_gem_context.c

+3 −3
Original line number Diff line number Diff line
@@ -1190,7 +1190,7 @@ static void set_ppgtt_barrier(void *data) 
{

	struct i915_address_space *old = data;



	if (INTEL_GEN(old->i915) < 8)

	if (GRAPHICS_VER(old->i915) < 8)

		gen6_ppgtt_unpin_all(i915_vm_to_ppgtt(old));



	i915_vm_close(old);
@@ -1436,7 +1436,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt, 
	context->max_eus_per_subslice = user->max_eus_per_subslice;



	/* Part specific restrictions. */

	if (IS_GEN(i915, 11)) {

	if (GRAPHICS_VER(i915) == 11) {

		unsigned int hw_s = hweight8(device->slice_mask);

		unsigned int hw_ss_per_s = hweight8(device->subslice_mask[0]);

		unsigned int req_s = hweight8(context->slice_mask);
@@ -1503,7 +1503,7 @@ static int set_sseu(struct i915_gem_context *ctx, 
	if (args->size < sizeof(user_sseu))

		return -EINVAL;



	if (!IS_GEN(i915, 11))

	if (GRAPHICS_VER(i915) != 11)

		return -ENODEV;



	if (copy_from_user(&user_sseu, u64_to_user_ptr(args->value),

drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c

+1 −1
Original line number Diff line number Diff line
@@ -209,7 +209,7 @@ static int i915_gem_object_get_pages_dmabuf(struct drm_i915_gem_object *obj) 
	if (IS_ERR(pages))

		return PTR_ERR(pages);



	sg_page_sizes = i915_sg_page_sizes(pages->sgl);

	sg_page_sizes = i915_sg_dma_sizes(pages->sgl);



	__i915_gem_object_set_pages(obj, pages, sg_page_sizes);

drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c

+5 −5
Original line number Diff line number Diff line
@@ -500,7 +500,7 @@ eb_validate_vma(struct i915_execbuffer *eb, 
	 * also covers all platforms with local memory.

	 */

	if (entry->relocation_count &&

	    INTEL_GEN(eb->i915) >= 12 && !IS_TIGERLAKE(eb->i915))

	    GRAPHICS_VER(eb->i915) >= 12 && !IS_TIGERLAKE(eb->i915))

		return -EINVAL;



	if (unlikely(entry->flags & eb->invalid_flags))
@@ -1439,7 +1439,7 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb, 


static bool reloc_can_use_engine(const struct intel_engine_cs *engine)

{

	return engine->class != VIDEO_DECODE_CLASS || !IS_GEN(engine->i915, 6);

	return engine->class != VIDEO_DECODE_CLASS || GRAPHICS_VER(engine->i915) != 6;

}



static u32 *reloc_gpu(struct i915_execbuffer *eb,
@@ -1671,7 +1671,7 @@ eb_relocate_entry(struct i915_execbuffer *eb, 
		 * batchbuffers.

		 */

		if (reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&

		    IS_GEN(eb->i915, 6)) {

		    GRAPHICS_VER(eb->i915) == 6) {

			err = i915_vma_bind(target->vma,

					    target->vma->obj->cache_level,

					    PIN_GLOBAL, NULL);
@@ -2332,7 +2332,7 @@ static int i915_reset_gen7_sol_offsets(struct i915_request *rq) 
	u32 *cs;

	int i;



	if (!IS_GEN(rq->engine->i915, 7) || rq->engine->id != RCS0) {

	if (GRAPHICS_VER(rq->engine->i915) != 7 || rq->engine->id != RCS0) {

		drm_dbg(&rq->engine->i915->drm, "sol reset is gen7/rcs only\n");

		return -EINVAL;

	}
@@ -3375,7 +3375,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, 


	eb.batch_flags = 0;

	if (args->flags & I915_EXEC_SECURE) {

		if (INTEL_GEN(i915) >= 11)

		if (GRAPHICS_VER(i915) >= 11)

			return -ENODEV;



		/* Return -EPERM to trigger fallback code on old binaries. */