Commit 2a50fc5f authored by Will Deacon's avatar Will Deacon Committed by Marc Zyngier
Browse files

KVM: arm64: Handle host stage-2 faults from 32-bit EL0 



When pKVM is enabled, host memory accesses are translated by an identity
mapping at stage-2, which is populated lazily in response to synchronous
exceptions from 64-bit EL1 and EL0.

Extend this handling to cover exceptions originating from 32-bit EL0 as
well. Although these are very unlikely to occur in practice, as the
kernel typically ensures that user pages are initialised before mapping
them in, drivers could still map previously untouched device pages into
userspace and expect things to work rather than panic the system.

Cc: Quentin Perret <qperret@google.com>
Cc: Marc Zyngier <maz@kernel.org>
Signed-off-by: default avatarWill Deacon <will@kernel.org>
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220427171332.13635-1-will@kernel.org
parent 21db8384

arch/arm64/kvm/hyp/nvhe/host.S

+9 −9
Original line number Diff line number Diff line
@@ -198,15 +198,15 @@ SYM_CODE_START(__kvm_hyp_host_vector) 
	invalid_host_el2_vect			// FIQ EL2h

	invalid_host_el2_vect			// Error EL2h



	host_el1_sync_vect			// Synchronous 64-bit EL1

	invalid_host_el1_vect			// IRQ 64-bit EL1

	invalid_host_el1_vect			// FIQ 64-bit EL1

	invalid_host_el1_vect			// Error 64-bit EL1



	invalid_host_el1_vect			// Synchronous 32-bit EL1

	invalid_host_el1_vect			// IRQ 32-bit EL1

	invalid_host_el1_vect			// FIQ 32-bit EL1

	invalid_host_el1_vect			// Error 32-bit EL1

	host_el1_sync_vect			// Synchronous 64-bit EL1/EL0

	invalid_host_el1_vect			// IRQ 64-bit EL1/EL0

	invalid_host_el1_vect			// FIQ 64-bit EL1/EL0

	invalid_host_el1_vect			// Error 64-bit EL1/EL0



	host_el1_sync_vect			// Synchronous 32-bit EL1/EL0

	invalid_host_el1_vect			// IRQ 32-bit EL1/EL0

	invalid_host_el1_vect			// FIQ 32-bit EL1/EL0

	invalid_host_el1_vect			// Error 32-bit EL1/EL0

SYM_CODE_END(__kvm_hyp_host_vector)



/*