Commit 2a3c17ed authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'riscv-for-linus-6.5-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux 

Pull RISC-V fixes from Palmer Dabbelt:

 - Fixes for a pair of kexec_file_load() failures

 - A fix to ensure the direct mapping is PMD-aligned

 - A fix for CPU feature detection on SMP=n

 - The MMIO ordering fences have been strengthened to ensure ordering
   WRT delay()

 - Fixes for a pair of -Wmissing-variable-declarations warnings

 - A fix to avoid PUD mappings in vmap on sv39

 - flush_cache_vmap() now flushes the TLB to avoid issues on systems
   that cache invalid mappings

* tag 'riscv-for-linus-6.5-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  riscv: Implement flush_cache_vmap()
  riscv: Do not allow vmap pud mappings for 3-level page table
  riscv: mm: fix 2 instances of -Wmissing-variable-declarations
  riscv,mmio: Fix readX()-to-delay() ordering
  riscv: Fix CPU feature detection with SMP disabled
  riscv: Start of DRAM should at least be aligned on PMD size for the direct mapping
  riscv/kexec: load initrd high in available memory
  riscv/kexec: handle R_RISCV_CALL_PLT relocation type
parents feb0eee9 7e381152

arch/riscv/include/asm/cacheflush.h

+4 −0
Original line number Diff line number Diff line
@@ -37,6 +37,10 @@ static inline void flush_dcache_page(struct page *page) 
#define flush_icache_user_page(vma, pg, addr, len) \

	flush_icache_mm(vma->vm_mm, 0)



#ifdef CONFIG_64BIT

#define flush_cache_vmap(start, end)	flush_tlb_kernel_range(start, end)

#endif



#ifndef CONFIG_SMP



#define flush_icache_all() local_flush_icache_all()

arch/riscv/include/asm/mmio.h

+8 −8
Original line number Diff line number Diff line
@@ -101,9 +101,9 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) 
 * Relaxed I/O memory access primitives. These follow the Device memory

 * ordering rules but do not guarantee any ordering relative to Normal memory

 * accesses.  These are defined to order the indicated access (either a read or

 * write) with all other I/O memory accesses. Since the platform specification

 * defines that all I/O regions are strongly ordered on channel 2, no explicit

 * fences are required to enforce this ordering.

 * write) with all other I/O memory accesses to the same peripheral. Since the

 * platform specification defines that all I/O regions are strongly ordered on

 * channel 0, no explicit fences are required to enforce this ordering.

 */

/* FIXME: These are now the same as asm-generic */

#define __io_rbr()		do {} while (0)
@@ -125,14 +125,14 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) 
#endif



/*

 * I/O memory access primitives. Reads are ordered relative to any

 * following Normal memory access. Writes are ordered relative to any prior

 * Normal memory access.  The memory barriers here are necessary as RISC-V

 * I/O memory access primitives.  Reads are ordered relative to any following

 * Normal memory read and delay() loop.  Writes are ordered relative to any

 * prior Normal memory write.  The memory barriers here are necessary as RISC-V

 * doesn't define any ordering between the memory space and the I/O space.

 */

#define __io_br()	do {} while (0)

#define __io_ar(v)	__asm__ __volatile__ ("fence i,r" : : : "memory")

#define __io_bw()	__asm__ __volatile__ ("fence w,o" : : : "memory")

#define __io_ar(v)	({ __asm__ __volatile__ ("fence i,ir" : : : "memory"); })

#define __io_bw()	({ __asm__ __volatile__ ("fence w,o" : : : "memory"); })

#define __io_aw()	mmiowb_set_pending()



#define readb(c)	({ u8  __v; __io_br(); __v = readb_cpu(c); __io_ar(__v); __v; })

arch/riscv/include/asm/pgtable.h

+2 −0
Original line number Diff line number Diff line
@@ -188,6 +188,8 @@ extern struct pt_alloc_ops pt_ops __initdata; 
#define PAGE_KERNEL_IO		__pgprot(_PAGE_IOREMAP)



extern pgd_t swapper_pg_dir[];

extern pgd_t trampoline_pg_dir[];

extern pgd_t early_pg_dir[];



#ifdef CONFIG_TRANSPARENT_HUGEPAGE

static inline int pmd_present(pmd_t pmd)

arch/riscv/include/asm/vmalloc.h

+3 −1
Original line number Diff line number Diff line
@@ -3,12 +3,14 @@ 


#ifdef CONFIG_HAVE_ARCH_HUGE_VMAP



extern bool pgtable_l4_enabled, pgtable_l5_enabled;



#define IOREMAP_MAX_ORDER (PUD_SHIFT)



#define arch_vmap_pud_supported arch_vmap_pud_supported

static inline bool arch_vmap_pud_supported(pgprot_t prot)

{

	return true;

	return pgtable_l4_enabled || pgtable_l5_enabled;

}



#define arch_vmap_pmd_supported arch_vmap_pmd_supported

arch/riscv/kernel/cpu.c

+5 −0
Original line number Diff line number Diff line
@@ -17,6 +17,11 @@ 
#include <asm/smp.h>

#include <asm/pgtable.h>



bool arch_match_cpu_phys_id(int cpu, u64 phys_id)

{

	return phys_id == cpuid_to_hartid_map(cpu);

}



/*

 * Returns the hart ID of the given device tree node, or -ENODEV if the node

 * isn't an enabled and valid RISC-V hart node.