Commit 2a252a0b authored by Horatiu Vultur's avatar Horatiu Vultur Committed by David S. Miller
Browse files

net: lan966x: Add registers used by taprio 



Add registers that are used by taprio to configure the HW.

Signed-off-by: default avatarHoratiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 3c83431f

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

+159 −0
Original line number Diff line number Diff line
@@ -1018,6 +1018,165 @@ enum lan966x_target { 
/*      QSYS:RES_CTRL:RES_CFG */

#define QSYS_RES_CFG(g)           __REG(TARGET_QSYS, 0, 1, 32768, g, 1024, 8, 0, 0, 1, 4)



/*      QSYS:TAS_CONFIG:TAS_CFG_CTRL */

#define QSYS_TAS_CFG_CTRL         __REG(TARGET_QSYS, 0, 1, 57372, 0, 1, 12, 0, 0, 1, 4)



#define QSYS_TAS_CFG_CTRL_LIST_NUM_MAX           GENMASK(27, 23)

#define QSYS_TAS_CFG_CTRL_LIST_NUM_MAX_SET(x)\

	FIELD_PREP(QSYS_TAS_CFG_CTRL_LIST_NUM_MAX, x)

#define QSYS_TAS_CFG_CTRL_LIST_NUM_MAX_GET(x)\

	FIELD_GET(QSYS_TAS_CFG_CTRL_LIST_NUM_MAX, x)



#define QSYS_TAS_CFG_CTRL_LIST_NUM               GENMASK(22, 18)

#define QSYS_TAS_CFG_CTRL_LIST_NUM_SET(x)\

	FIELD_PREP(QSYS_TAS_CFG_CTRL_LIST_NUM, x)

#define QSYS_TAS_CFG_CTRL_LIST_NUM_GET(x)\

	FIELD_GET(QSYS_TAS_CFG_CTRL_LIST_NUM, x)



#define QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q        BIT(17)

#define QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q_SET(x)\

	FIELD_PREP(QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q, x)

#define QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q_GET(x)\

	FIELD_GET(QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q, x)



#define QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM          GENMASK(16, 5)

#define QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM_SET(x)\

	FIELD_PREP(QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM, x)

#define QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM_GET(x)\

	FIELD_GET(QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM, x)



/*      QSYS:TAS_CONFIG:TAS_GATE_STATE_CTRL */

#define QSYS_TAS_GS_CTRL          __REG(TARGET_QSYS, 0, 1, 57372, 0, 1, 12, 4, 0, 1, 4)



#define QSYS_TAS_GS_CTRL_HSCH_POS                GENMASK(2, 0)

#define QSYS_TAS_GS_CTRL_HSCH_POS_SET(x)\

	FIELD_PREP(QSYS_TAS_GS_CTRL_HSCH_POS, x)

#define QSYS_TAS_GS_CTRL_HSCH_POS_GET(x)\

	FIELD_GET(QSYS_TAS_GS_CTRL_HSCH_POS, x)



/*      QSYS:TAS_CONFIG:TAS_STATEMACHINE_CFG */

#define QSYS_TAS_STM_CFG          __REG(TARGET_QSYS, 0, 1, 57372, 0, 1, 12, 8, 0, 1, 4)



#define QSYS_TAS_STM_CFG_REVISIT_DLY             GENMASK(7, 0)

#define QSYS_TAS_STM_CFG_REVISIT_DLY_SET(x)\

	FIELD_PREP(QSYS_TAS_STM_CFG_REVISIT_DLY, x)

#define QSYS_TAS_STM_CFG_REVISIT_DLY_GET(x)\

	FIELD_GET(QSYS_TAS_STM_CFG_REVISIT_DLY, x)



/*      QSYS:TAS_PROFILE_CFG:TAS_PROFILE_CONFIG */

#define QSYS_TAS_PROFILE_CFG(g)   __REG(TARGET_QSYS, 0, 1, 30720, g, 16, 64, 32, 0, 1, 4)



#define QSYS_TAS_PROFILE_CFG_PORT_NUM            GENMASK(21, 19)

#define QSYS_TAS_PROFILE_CFG_PORT_NUM_SET(x)\

	FIELD_PREP(QSYS_TAS_PROFILE_CFG_PORT_NUM, x)

#define QSYS_TAS_PROFILE_CFG_PORT_NUM_GET(x)\

	FIELD_GET(QSYS_TAS_PROFILE_CFG_PORT_NUM, x)



#define QSYS_TAS_PROFILE_CFG_LINK_SPEED          GENMASK(18, 16)

#define QSYS_TAS_PROFILE_CFG_LINK_SPEED_SET(x)\

	FIELD_PREP(QSYS_TAS_PROFILE_CFG_LINK_SPEED, x)

#define QSYS_TAS_PROFILE_CFG_LINK_SPEED_GET(x)\

	FIELD_GET(QSYS_TAS_PROFILE_CFG_LINK_SPEED, x)



/*      QSYS:TAS_LIST_CFG:TAS_BASE_TIME_NSEC */

#define QSYS_TAS_BT_NSEC          __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 0, 0, 1, 4)



#define QSYS_TAS_BT_NSEC_NSEC                    GENMASK(29, 0)

#define QSYS_TAS_BT_NSEC_NSEC_SET(x)\

	FIELD_PREP(QSYS_TAS_BT_NSEC_NSEC, x)

#define QSYS_TAS_BT_NSEC_NSEC_GET(x)\

	FIELD_GET(QSYS_TAS_BT_NSEC_NSEC, x)



/*      QSYS:TAS_LIST_CFG:TAS_BASE_TIME_SEC_LSB */

#define QSYS_TAS_BT_SEC_LSB       __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 4, 0, 1, 4)



/*      QSYS:TAS_LIST_CFG:TAS_BASE_TIME_SEC_MSB */

#define QSYS_TAS_BT_SEC_MSB       __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 8, 0, 1, 4)



#define QSYS_TAS_BT_SEC_MSB_SEC_MSB              GENMASK(15, 0)

#define QSYS_TAS_BT_SEC_MSB_SEC_MSB_SET(x)\

	FIELD_PREP(QSYS_TAS_BT_SEC_MSB_SEC_MSB, x)

#define QSYS_TAS_BT_SEC_MSB_SEC_MSB_GET(x)\

	FIELD_GET(QSYS_TAS_BT_SEC_MSB_SEC_MSB, x)



/*      QSYS:TAS_LIST_CFG:TAS_CYCLE_TIME_CFG */

#define QSYS_TAS_CT_CFG           __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 24, 0, 1, 4)



/*      QSYS:TAS_LIST_CFG:TAS_STARTUP_CFG */

#define QSYS_TAS_STARTUP_CFG      __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 28, 0, 1, 4)



#define QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX        GENMASK(27, 23)

#define QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX_SET(x)\

	FIELD_PREP(QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX, x)

#define QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX_GET(x)\

	FIELD_GET(QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX, x)



/*      QSYS:TAS_LIST_CFG:TAS_LIST_CFG */

#define QSYS_TAS_LIST_CFG         __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 32, 0, 1, 4)



#define QSYS_TAS_LIST_CFG_LIST_BASE_ADDR         GENMASK(11, 0)

#define QSYS_TAS_LIST_CFG_LIST_BASE_ADDR_SET(x)\

	FIELD_PREP(QSYS_TAS_LIST_CFG_LIST_BASE_ADDR, x)

#define QSYS_TAS_LIST_CFG_LIST_BASE_ADDR_GET(x)\

	FIELD_GET(QSYS_TAS_LIST_CFG_LIST_BASE_ADDR, x)



/*      QSYS:TAS_LIST_CFG:TAS_LIST_STATE */

#define QSYS_TAS_LST              __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 36, 0, 1, 4)



#define QSYS_TAS_LST_LIST_STATE                  GENMASK(2, 0)

#define QSYS_TAS_LST_LIST_STATE_SET(x)\

	FIELD_PREP(QSYS_TAS_LST_LIST_STATE, x)

#define QSYS_TAS_LST_LIST_STATE_GET(x)\

	FIELD_GET(QSYS_TAS_LST_LIST_STATE, x)



/*      QSYS:TAS_GCL_CFG:TAS_GCL_CTRL_CFG */

#define QSYS_TAS_GCL_CT_CFG       __REG(TARGET_QSYS, 0, 1, 27968, 0, 1, 16, 0, 0, 1, 4)



#define QSYS_TAS_GCL_CT_CFG_HSCH_POS             GENMASK(12, 10)

#define QSYS_TAS_GCL_CT_CFG_HSCH_POS_SET(x)\

	FIELD_PREP(QSYS_TAS_GCL_CT_CFG_HSCH_POS, x)

#define QSYS_TAS_GCL_CT_CFG_HSCH_POS_GET(x)\

	FIELD_GET(QSYS_TAS_GCL_CT_CFG_HSCH_POS, x)



#define QSYS_TAS_GCL_CT_CFG_GATE_STATE           GENMASK(9, 2)

#define QSYS_TAS_GCL_CT_CFG_GATE_STATE_SET(x)\

	FIELD_PREP(QSYS_TAS_GCL_CT_CFG_GATE_STATE, x)

#define QSYS_TAS_GCL_CT_CFG_GATE_STATE_GET(x)\

	FIELD_GET(QSYS_TAS_GCL_CT_CFG_GATE_STATE, x)



#define QSYS_TAS_GCL_CT_CFG_OP_TYPE              GENMASK(1, 0)

#define QSYS_TAS_GCL_CT_CFG_OP_TYPE_SET(x)\

	FIELD_PREP(QSYS_TAS_GCL_CT_CFG_OP_TYPE, x)

#define QSYS_TAS_GCL_CT_CFG_OP_TYPE_GET(x)\

	FIELD_GET(QSYS_TAS_GCL_CT_CFG_OP_TYPE, x)



/*      QSYS:TAS_GCL_CFG:TAS_GCL_CTRL_CFG2 */

#define QSYS_TAS_GCL_CT_CFG2      __REG(TARGET_QSYS, 0, 1, 27968, 0, 1, 16, 4, 0, 1, 4)



#define QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE        GENMASK(15, 12)

#define QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE_SET(x)\

	FIELD_PREP(QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE, x)

#define QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE_GET(x)\

	FIELD_GET(QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE, x)



#define QSYS_TAS_GCL_CT_CFG2_NEXT_GCL            GENMASK(11, 0)

#define QSYS_TAS_GCL_CT_CFG2_NEXT_GCL_SET(x)\

	FIELD_PREP(QSYS_TAS_GCL_CT_CFG2_NEXT_GCL, x)

#define QSYS_TAS_GCL_CT_CFG2_NEXT_GCL_GET(x)\

	FIELD_GET(QSYS_TAS_GCL_CT_CFG2_NEXT_GCL, x)



/*      QSYS:TAS_GCL_CFG:TAS_GCL_TIME_CFG */

#define QSYS_TAS_GCL_TM_CFG       __REG(TARGET_QSYS, 0, 1, 27968, 0, 1, 16, 8, 0, 1, 4)



/*      QSYS:HSCH_TAS_STATE:TAS_GATE_STATE */

#define QSYS_TAS_GATE_STATE       __REG(TARGET_QSYS, 0, 1, 28004, 0, 1, 4, 0, 0, 1, 4)



#define QSYS_TAS_GATE_STATE_TAS_GATE_STATE       GENMASK(7, 0)

#define QSYS_TAS_GATE_STATE_TAS_GATE_STATE_SET(x)\

	FIELD_PREP(QSYS_TAS_GATE_STATE_TAS_GATE_STATE, x)

#define QSYS_TAS_GATE_STATE_TAS_GATE_STATE_GET(x)\

	FIELD_GET(QSYS_TAS_GATE_STATE_TAS_GATE_STATE, x)



/*      REW:PORT:PORT_VLAN_CFG */

#define REW_PORT_VLAN_CFG(g)      __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 0, 0, 1, 4)