Commit 2a210e6a authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2023-03-15' of... 

Merge tag 'drm-intel-fixes-2023-03-15' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-fixes

drm/i915 fixes for v6.3-rc3:
- Fix hwmon PL1 power limit enabling
- Fix audio ELD handling for DP MST
- Fix PSR io and wake line calculations
- Fix DG2 HDMI modes with 267.30 and 319.89 MHz pixel clocks
- Fix SSEU subslice out-of-bounds access
- Fix misuse of non-idle barriers as fence trackers

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/87r0tq5nyn.fsf@intel.com
parents bcd9d56f e0e6b416

drivers/gpu/drm/i915/display/intel_display_types.h

+2 −0
Original line number Diff line number Diff line
@@ -1631,6 +1631,8 @@ struct intel_psr { 
	bool psr2_sel_fetch_cff_enabled;

	bool req_psr2_sdp_prior_scanline;

	u8 sink_sync_latency;

	u8 io_wake_lines;

	u8 fast_wake_lines;

	ktime_t last_entry_attempt;

	ktime_t last_exit;

	bool sink_not_reliable;

drivers/gpu/drm/i915/display/intel_dp_mst.c

+16 −9
Original line number Diff line number Diff line
@@ -265,6 +265,19 @@ static int intel_dp_mst_update_slots(struct intel_encoder *encoder, 
	return 0;

}



static bool intel_dp_mst_has_audio(const struct drm_connector_state *conn_state)

{

	const struct intel_digital_connector_state *intel_conn_state =

		to_intel_digital_connector_state(conn_state);

	struct intel_connector *connector =

		to_intel_connector(conn_state->connector);



	if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)

		return connector->port->has_audio;

	else

		return intel_conn_state->force_audio == HDMI_AUDIO_ON;

}



static int intel_dp_mst_compute_config(struct intel_encoder *encoder,

				       struct intel_crtc_state *pipe_config,

				       struct drm_connector_state *conn_state)
@@ -272,10 +285,6 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, 
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);

	struct intel_dp *intel_dp = &intel_mst->primary->dp;

	struct intel_connector *connector =

		to_intel_connector(conn_state->connector);

	struct intel_digital_connector_state *intel_conn_state =

		to_intel_digital_connector_state(conn_state);

	const struct drm_display_mode *adjusted_mode =

		&pipe_config->hw.adjusted_mode;

	struct link_config_limits limits;
@@ -287,11 +296,9 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, 
	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;

	pipe_config->has_pch_encoder = false;



	if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)

		pipe_config->has_audio = connector->port->has_audio;

	else

	pipe_config->has_audio =

			intel_conn_state->force_audio == HDMI_AUDIO_ON;

		intel_dp_mst_has_audio(conn_state) &&

		intel_audio_compute_config(encoder, pipe_config, conn_state);



	/*

	 * for MST we always configure max link bw - the spec doesn't

drivers/gpu/drm/i915/display/intel_psr.c

+61 −17
Original line number Diff line number Diff line
@@ -542,6 +542,14 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) 
	val |= EDP_PSR2_FRAME_BEFORE_SU(max_t(u8, intel_dp->psr.sink_sync_latency + 1, 2));

	val |= intel_psr2_get_tp_time(intel_dp);



	if (DISPLAY_VER(dev_priv) >= 12) {

		if (intel_dp->psr.io_wake_lines < 9 &&

		    intel_dp->psr.fast_wake_lines < 9)

			val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2;

		else

			val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_3;

	}



	/* Wa_22012278275:adl-p */

	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) {

		static const u8 map[] = {
@@ -558,31 +566,21 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) 
		 * Still using the default IO_BUFFER_WAKE and FAST_WAKE, see

		 * comments bellow for more information

		 */

		u32 tmp, lines = 7;



		val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2;

		u32 tmp;



		tmp = map[lines - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES];

		tmp = map[intel_dp->psr.io_wake_lines - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES];

		tmp = tmp << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT;

		val |= tmp;



		tmp = map[lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES];

		tmp = map[intel_dp->psr.fast_wake_lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES];

		tmp = tmp << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT;

		val |= tmp;

	} else if (DISPLAY_VER(dev_priv) >= 12) {

		/*

		 * TODO: 7 lines of IO_BUFFER_WAKE and FAST_WAKE are default

		 * values from BSpec. In order to setting an optimal power

		 * consumption, lower than 4k resolution mode needs to decrease

		 * IO_BUFFER_WAKE and FAST_WAKE. And higher than 4K resolution

		 * mode needs to increase IO_BUFFER_WAKE and FAST_WAKE.

		 */

		val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2;

		val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(7);

		val |= TGL_EDP_PSR2_FAST_WAKE(7);

		val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines);

		val |= TGL_EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake_lines);

	} else if (DISPLAY_VER(dev_priv) >= 9) {

		val |= EDP_PSR2_IO_BUFFER_WAKE(7);

		val |= EDP_PSR2_FAST_WAKE(7);

		val |= EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines);

		val |= EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake_lines);

	}



	if (intel_dp->psr.req_psr2_sdp_prior_scanline)
@@ -842,6 +840,46 @@ static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_d 
	return true;

}



static bool _compute_psr2_wake_times(struct intel_dp *intel_dp,

				     struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *i915 = dp_to_i915(intel_dp);

	int io_wake_lines, io_wake_time, fast_wake_lines, fast_wake_time;

	u8 max_wake_lines;



	if (DISPLAY_VER(i915) >= 12) {

		io_wake_time = 42;

		/*

		 * According to Bspec it's 42us, but based on testing

		 * it is not enough -> use 45 us.

		 */

		fast_wake_time = 45;

		max_wake_lines = 12;

	} else {

		io_wake_time = 50;

		fast_wake_time = 32;

		max_wake_lines = 8;

	}



	io_wake_lines = intel_usecs_to_scanlines(

		&crtc_state->uapi.adjusted_mode, io_wake_time);

	fast_wake_lines = intel_usecs_to_scanlines(

		&crtc_state->uapi.adjusted_mode, fast_wake_time);



	if (io_wake_lines > max_wake_lines ||

	    fast_wake_lines > max_wake_lines)

		return false;



	if (i915->params.psr_safest_params)

		io_wake_lines = fast_wake_lines = max_wake_lines;



	/* According to Bspec lower limit should be set as 7 lines. */

	intel_dp->psr.io_wake_lines = max(io_wake_lines, 7);

	intel_dp->psr.fast_wake_lines = max(fast_wake_lines, 7);



	return true;

}



static bool intel_psr2_config_valid(struct intel_dp *intel_dp,

				    struct intel_crtc_state *crtc_state)

{
@@ -936,6 +974,12 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, 
		return false;

	}



	if (!_compute_psr2_wake_times(intel_dp, crtc_state)) {

		drm_dbg_kms(&dev_priv->drm,

			    "PSR2 not enabled, Unable to use long enough wake times\n");

		return false;

	}



	if (HAS_PSR2_SEL_FETCH(dev_priv)) {

		if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) &&

		    !HAS_PSR_HW_TRACKING(dev_priv)) {

drivers/gpu/drm/i915/display/intel_snps_phy.c

+62 −0
Original line number Diff line number Diff line
@@ -1419,6 +1419,36 @@ static const struct intel_mpllb_state dg2_hdmi_262750 = { 
		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

};



static const struct intel_mpllb_state dg2_hdmi_267300 = {

	.clock = 267300,

	.ref_control =

		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

	.mpllb_cp =

		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |

		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |

		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

	.mpllb_div =

		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |

		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),

	.mpllb_div2 =

		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 74) |

		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

	.mpllb_fracn1 =

		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

	.mpllb_fracn2 =

		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 30146) |

		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 36699),

	.mpllb_sscen =

		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

};



static const struct intel_mpllb_state dg2_hdmi_268500 = {

	.clock = 268500,

	.ref_control =
@@ -1509,6 +1539,36 @@ static const struct intel_mpllb_state dg2_hdmi_241500 = { 
		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

};



static const struct intel_mpllb_state dg2_hdmi_319890 = {

	.clock = 319890,

	.ref_control =

		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

	.mpllb_cp =

		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |

		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |

		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

	.mpllb_div =

		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |

		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),

	.mpllb_div2 =

		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 94) |

		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

	.mpllb_fracn1 =

		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

	.mpllb_fracn2 =

		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 64094) |

		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13631),

	.mpllb_sscen =

		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

};



static const struct intel_mpllb_state dg2_hdmi_497750 = {

	.clock = 497750,

	.ref_control =
@@ -1696,8 +1756,10 @@ static const struct intel_mpllb_state * const dg2_hdmi_tables[] = { 
	&dg2_hdmi_209800,

	&dg2_hdmi_241500,

	&dg2_hdmi_262750,

	&dg2_hdmi_267300,

	&dg2_hdmi_268500,

	&dg2_hdmi_296703,

	&dg2_hdmi_319890,

	&dg2_hdmi_497750,

	&dg2_hdmi_592000,

	&dg2_hdmi_593407,

drivers/gpu/drm/i915/gt/intel_sseu.h

+1 −1
Original line number Diff line number Diff line
@@ -27,7 +27,7 @@ struct drm_printer; 
 * is only relevant to pre-Xe_HP platforms (Xe_HP and beyond use the

 * I915_MAX_SS_FUSE_BITS value below).

 */

#define GEN_MAX_SS_PER_HSW_SLICE	6

#define GEN_MAX_SS_PER_HSW_SLICE	8



/*

 * Maximum number of 32-bit registers used by hardware to express the