Commit 29ae1118 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amd/pp: Remove unnecessary forward declaration 



Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 45313e5f

drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

+41 −43
Original line number Diff line number Diff line
@@ -75,8 +75,6 @@ static const uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2}; 
#define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK                                                        0x000000F0L

#define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK                                                        0x00000700L

#define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK                                                        0xFFFFF000L

static int vega10_force_clock_level(struct pp_hwmgr *hwmgr,

		enum pp_clock_type type, uint32_t mask);



static const ULONG PhwVega10_Magic = (ULONG)(PHM_VIslands_Magic);
@@ -4095,6 +4093,47 @@ static void vega10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) 
	}

}



static int vega10_force_clock_level(struct pp_hwmgr *hwmgr,

		enum pp_clock_type type, uint32_t mask)

{

	struct vega10_hwmgr *data = hwmgr->backend;



	switch (type) {

	case PP_SCLK:

		data->smc_state_table.gfx_boot_level = mask ? (ffs(mask) - 1) : 0;

		data->smc_state_table.gfx_max_level = mask ? (fls(mask) - 1) : 0;



		PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),

			"Failed to upload boot level to lowest!",

			return -EINVAL);



		PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),

			"Failed to upload dpm max level to highest!",

			return -EINVAL);

		break;



	case PP_MCLK:

		data->smc_state_table.mem_boot_level = mask ? (ffs(mask) - 1) : 0;

		data->smc_state_table.mem_max_level = mask ? (fls(mask) - 1) : 0;



		PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),

			"Failed to upload boot level to lowest!",

			return -EINVAL);



		PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),

			"Failed to upload dpm max level to highest!",

			return -EINVAL);



		break;



	case PP_PCIE:

	default:

		break;

	}



	return 0;

}



static int vega10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,

				enum amd_dpm_forced_level level)

{
@@ -4381,47 +4420,6 @@ static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, 
	return result;

}



static int vega10_force_clock_level(struct pp_hwmgr *hwmgr,

		enum pp_clock_type type, uint32_t mask)

{

	struct vega10_hwmgr *data = hwmgr->backend;



	switch (type) {

	case PP_SCLK:

		data->smc_state_table.gfx_boot_level = mask ? (ffs(mask) - 1) : 0;

		data->smc_state_table.gfx_max_level = mask ? (fls(mask) - 1) : 0;



		PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),

			"Failed to upload boot level to lowest!",

			return -EINVAL);



		PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),

			"Failed to upload dpm max level to highest!",

			return -EINVAL);

		break;



	case PP_MCLK:

		data->smc_state_table.mem_boot_level = mask ? (ffs(mask) - 1) : 0;

		data->smc_state_table.mem_max_level = mask ? (fls(mask) - 1) : 0;



		PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),

			"Failed to upload boot level to lowest!",

			return -EINVAL);



		PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),

			"Failed to upload dpm max level to highest!",

			return -EINVAL);



		break;



	case PP_PCIE:

	default:

		break;

	}



	return 0;

}



static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,

		enum pp_clock_type type, char *buf)

{