Commit 299d5dca authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events intel: Update events for SkylakeX

The change:

  https://github.com/intel/event-converter-for-linux-perf/commit/fc680410402e394eed6a1ebd909c9f649d3ed3ef



moved certain "other" type of events in to the cache topic. Update the
perf JSON files for this change.

Reviewed-by: default avatarXing Zhengjun <zhengjun.xing@linux.intel.com>
Signed-off-by: default avatarIan Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.garry@huawei.com>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Link: https://lore.kernel.org/r/20220317182858.484474-6-irogers@google.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent fd143118
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+36 −0
Original line number Diff line number Diff line
@@ -1686,5 +1686,41 @@
        "PublicDescription": "Counts the number of cache line split locks sent to the uncore.",
        "SampleAfterValue": "100003",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "Number of PREFETCHNTA instructions executed.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x32",
        "EventName": "SW_PREFETCH_ACCESS.NTA",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Number of PREFETCHW instructions executed.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x32",
        "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
        "SampleAfterValue": "2000003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Number of PREFETCHT0 instructions executed.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x32",
        "EventName": "SW_PREFETCH_ACCESS.T0",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x32",
        "EventName": "SW_PREFETCH_ACCESS.T1_T2",
        "SampleAfterValue": "2000003",
        "UMask": "0x4"
    }
]
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+0 −36
Original line number Diff line number Diff line
@@ -76,41 +76,5 @@
        "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Number of PREFETCHNTA instructions executed.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x32",
        "EventName": "SW_PREFETCH_ACCESS.NTA",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Number of PREFETCHW instructions executed.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x32",
        "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
        "SampleAfterValue": "2000003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Number of PREFETCHT0 instructions executed.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x32",
        "EventName": "SW_PREFETCH_ACCESS.T0",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x32",
        "EventName": "SW_PREFETCH_ACCESS.T1_T2",
        "SampleAfterValue": "2000003",
        "UMask": "0x4"
    }
]
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