Commit 296d5a17 authored by Babu Moger's avatar Babu Moger Committed by Paolo Bonzini
Browse files

KVM: SEV-ES: Use V_TSC_AUX if available instead of RDTSC/MSR_TSC_AUX intercepts 



The TSC_AUX virtualization feature allows AMD SEV-ES guests to securely use
TSC_AUX (auxiliary time stamp counter data) in the RDTSCP and RDPID
instructions. The TSC_AUX value is set using the WRMSR instruction to the
TSC_AUX MSR (0xC0000103). It is read by the RDMSR, RDTSCP and RDPID
instructions. If the read/write of the TSC_AUX MSR is intercepted, then
RDTSCP and RDPID must also be intercepted when TSC_AUX virtualization
is present. However, the RDPID instruction can't be intercepted. This means
that when TSC_AUX virtualization is present, RDTSCP and TSC_AUX MSR
read/write must not be intercepted for SEV-ES (or SEV-SNP) guests.

Signed-off-by: default avatarBabu Moger <babu.moger@amd.com>
Message-Id: <165040164424.1399644.13833277687385156344.stgit@bmoger-ubuntu>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent f3090339

arch/x86/include/asm/cpufeatures.h

+1 −1
Original line number Diff line number Diff line
@@ -405,7 +405,7 @@ 
#define X86_FEATURE_SEV			(19*32+ 1) /* AMD Secure Encrypted Virtualization */

#define X86_FEATURE_VM_PAGE_FLUSH	(19*32+ 2) /* "" VM Page Flush MSR is supported */

#define X86_FEATURE_SEV_ES		(19*32+ 3) /* AMD Secure Encrypted Virtualization - Encrypted State */

#define X86_FEATURE_V_TSC_AUX		(19*32+ 9) /* Virtual TSC_AUX */

#define X86_FEATURE_V_TSC_AUX		(19*32+ 9) /* "" Virtual TSC_AUX */

#define X86_FEATURE_SME_COHERENT	(19*32+10) /* "" AMD hardware-enforced cache coherency */



/*

arch/x86/kvm/svm/sev.c

+8 −0
Original line number Diff line number Diff line
@@ -2926,6 +2926,14 @@ void sev_es_init_vmcb(struct vcpu_svm *svm) 
	set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);

	set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);

	set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 1, 1);



	if (boot_cpu_has(X86_FEATURE_V_TSC_AUX) &&

	    (guest_cpuid_has(&svm->vcpu, X86_FEATURE_RDTSCP) ||

	     guest_cpuid_has(&svm->vcpu, X86_FEATURE_RDPID))) {

		set_msr_interception(vcpu, svm->msrpm, MSR_TSC_AUX, 1, 1);

		if (guest_cpuid_has(&svm->vcpu, X86_FEATURE_RDTSCP))

			svm_clr_intercept(svm, INTERCEPT_RDTSCP);

	}

}



void sev_es_vcpu_reset(struct vcpu_svm *svm)

arch/x86/kvm/svm/svm.c

+1 −0
Original line number Diff line number Diff line
@@ -99,6 +99,7 @@ static const struct svm_direct_access_msrs { 
	{ .index = MSR_EFER,				.always = false },

	{ .index = MSR_IA32_CR_PAT,			.always = false },

	{ .index = MSR_AMD64_SEV_ES_GHCB,		.always = true  },

	{ .index = MSR_TSC_AUX,				.always = false },

	{ .index = MSR_INVALID,				.always = false },

};

arch/x86/kvm/svm/svm.h

+1 −1
Original line number Diff line number Diff line
@@ -29,7 +29,7 @@ 
#define	IOPM_SIZE PAGE_SIZE * 3

#define	MSRPM_SIZE PAGE_SIZE * 2



#define MAX_DIRECT_ACCESS_MSRS	20

#define MAX_DIRECT_ACCESS_MSRS	21

#define MSRPM_OFFSETS	16

extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;

extern bool npt_enabled;