Commit 2948ce70 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'remotes/lorenzo/pci/dwc' 

- Don't ioremap NULL when DT lacks ATU resource (Tim Harvey)

- Drop redundant qcom-ep error message for platform_get_irq_byname()
  failure (Krzysztof Wilczyński)

- Add i.MX8MM support (Richard Zhu)

- Use DWC common ops instead of layerscape-specific link-up functions (Hou
  Zhiqiang)

* remotes/lorenzo/pci/dwc:
  PCI: layerscape: Change to use the DWC common link-up check function
  PCI: imx: Add the imx8mm pcie support
  dt-bindings: imx6q-pcie: Add PHY phandles and name properties
  PCI: qcom-ep: Remove surplus dev_err() when using platform_get_irq_byname()
  PCI: dwc: Do not remap invalid res
parents c5f62d30 d23f0c11

Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml

+6 −0
Original line number Diff line number Diff line
@@ -127,6 +127,12 @@ properties: 
    enum: [1, 2, 3, 4]

    default: 1



  phys:

    maxItems: 1



  phy-names:

    const: pcie-phy



  reset-gpio:

    description: Should specify the GPIO for controlling the PCI bus device

      reset signal. It's not polarity aware and defaults to active-low reset

drivers/pci/controller/dwc/pci-imx6.c

+73 −8
Original line number Diff line number Diff line
@@ -29,6 +29,7 @@ 
#include <linux/types.h>

#include <linux/interrupt.h>

#include <linux/reset.h>

#include <linux/phy/phy.h>

#include <linux/pm_domain.h>

#include <linux/pm_runtime.h>
@@ -49,6 +50,7 @@ enum imx6_pcie_variants { 
	IMX6QP,

	IMX7D,

	IMX8MQ,

	IMX8MM,

};



#define IMX6_PCIE_FLAG_IMX6_PHY			BIT(0)
@@ -88,6 +90,7 @@ struct imx6_pcie { 
	struct device		*pd_pcie;

	/* power domain for pcie phy */

	struct device		*pd_pcie_phy;

	struct phy		*phy;

	const struct imx6_pcie_drvdata *drvdata;

};
@@ -372,6 +375,8 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) 
	case IMX7D:

	case IMX8MQ:

		reset_control_assert(imx6_pcie->pciephy_reset);

		fallthrough;

	case IMX8MM:

		reset_control_assert(imx6_pcie->apps_reset);

		break;

	case IMX6SX:
@@ -407,7 +412,8 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) 


static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie)

{

	WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ);

	WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ &&

		imx6_pcie->drvdata->variant != IMX8MM);

	return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;

}
@@ -446,6 +452,11 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) 
		break;

	case IMX7D:

		break;

	case IMX8MM:

		ret = clk_prepare_enable(imx6_pcie->pcie_aux);

		if (ret)

			dev_err(dev, "unable to enable pcie_aux clock\n");

		break;

	case IMX8MQ:

		ret = clk_prepare_enable(imx6_pcie->pcie_aux);

		if (ret) {
@@ -522,6 +533,14 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) 
		goto err_ref_clk;

	}



	switch (imx6_pcie->drvdata->variant) {

	case IMX8MM:

		if (phy_power_on(imx6_pcie->phy))

			dev_err(dev, "unable to power on PHY\n");

		break;

	default:

		break;

	}

	/* allow the clocks to stabilize */

	usleep_range(200, 500);
@@ -538,6 +557,10 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) 
	case IMX8MQ:

		reset_control_deassert(imx6_pcie->pciephy_reset);

		break;

	case IMX8MM:

		if (phy_init(imx6_pcie->phy))

			dev_err(dev, "waiting for phy ready timeout!\n");

		break;

	case IMX7D:

		reset_control_deassert(imx6_pcie->pciephy_reset);
@@ -614,6 +637,12 @@ static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie) 
static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)

{

	switch (imx6_pcie->drvdata->variant) {

	case IMX8MM:

		/*

		 * The PHY initialization had been done in the PHY

		 * driver, break here directly.

		 */

		break;

	case IMX8MQ:

		/*

		 * TODO: Currently this code assumes external
@@ -753,6 +782,7 @@ static void imx6_pcie_ltssm_enable(struct device *dev) 
		break;

	case IMX7D:

	case IMX8MQ:

	case IMX8MM:

		reset_control_deassert(imx6_pcie->apps_reset);

		break;

	}
@@ -871,6 +901,7 @@ static void imx6_pcie_ltssm_disable(struct device *dev) 
				   IMX6Q_GPR12_PCIE_CTL_2, 0);

		break;

	case IMX7D:

	case IMX8MM:

		reset_control_assert(imx6_pcie->apps_reset);

		break;

	default:
@@ -930,6 +961,7 @@ static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie) 
				   IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);

		break;

	case IMX8MQ:

	case IMX8MM:

		clk_disable_unprepare(imx6_pcie->pcie_aux);

		break;

	default:
@@ -945,8 +977,16 @@ static int imx6_pcie_suspend_noirq(struct device *dev) 
		return 0;



	imx6_pcie_pm_turnoff(imx6_pcie);

	imx6_pcie_clk_disable(imx6_pcie);

	imx6_pcie_ltssm_disable(dev);

	imx6_pcie_clk_disable(imx6_pcie);

	switch (imx6_pcie->drvdata->variant) {

	case IMX8MM:

		if (phy_power_off(imx6_pcie->phy))

			dev_err(dev, "unable to power off PHY\n");

		break;

	default:

		break;

	}



	return 0;

}
@@ -1043,11 +1083,6 @@ static int imx6_pcie_probe(struct platform_device *pdev) 
	}



	/* Fetch clocks */

	imx6_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy");

	if (IS_ERR(imx6_pcie->pcie_phy))

		return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_phy),

				     "pcie_phy clock source missing or invalid\n");



	imx6_pcie->pcie_bus = devm_clk_get(dev, "pcie_bus");

	if (IS_ERR(imx6_pcie->pcie_bus))

		return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_bus),
@@ -1089,10 +1124,35 @@ static int imx6_pcie_probe(struct platform_device *pdev) 
			dev_err(dev, "Failed to get PCIE APPS reset control\n");

			return PTR_ERR(imx6_pcie->apps_reset);

		}

		break;

	case IMX8MM:

		imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux");

		if (IS_ERR(imx6_pcie->pcie_aux))

			return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux),

					     "pcie_aux clock source missing or invalid\n");

		imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev,

									 "apps");

		if (IS_ERR(imx6_pcie->apps_reset))

			return dev_err_probe(dev, PTR_ERR(imx6_pcie->apps_reset),

					     "failed to get pcie apps reset control\n");



		imx6_pcie->phy = devm_phy_get(dev, "pcie-phy");

		if (IS_ERR(imx6_pcie->phy))

			return dev_err_probe(dev, PTR_ERR(imx6_pcie->phy),

					     "failed to get pcie phy\n");



		break;

	default:

		break;

	}

	/* Don't fetch the pcie_phy clock, if it has abstract PHY driver */

	if (imx6_pcie->phy == NULL) {

		imx6_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy");

		if (IS_ERR(imx6_pcie->pcie_phy))

			return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_phy),

					     "pcie_phy clock source missing or invalid\n");

	}





	/* Grab turnoff reset */

	imx6_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff");
@@ -1202,6 +1262,10 @@ static const struct imx6_pcie_drvdata drvdata[] = { 
	[IMX8MQ] = {

		.variant = IMX8MQ,

	},

	[IMX8MM] = {

		.variant = IMX8MM,

		.flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,

	},

};



static const struct of_device_id imx6_pcie_of_match[] = {
@@ -1210,6 +1274,7 @@ static const struct of_device_id imx6_pcie_of_match[] = { 
	{ .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], },

	{ .compatible = "fsl,imx7d-pcie",  .data = &drvdata[IMX7D],  },

	{ .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], },

	{ .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], },

	{},

};

drivers/pci/controller/dwc/pci-layerscape.c

+11 −141
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 
 * PCIe host controller driver for Freescale Layerscape SoCs

 *

 * Copyright (C) 2014 Freescale Semiconductor.

 * Copyright 2021 NXP

 *

 * Author: Minghuan Lian <Minghuan.Lian@freescale.com>

 */
@@ -22,12 +23,6 @@ 


#include "pcie-designware.h"



/* PEX1/2 Misc Ports Status Register */

#define SCFG_PEXMSCPORTSR(pex_idx)	(0x94 + (pex_idx) * 4)

#define LTSSM_STATE_SHIFT	20

#define LTSSM_STATE_MASK	0x3f

#define LTSSM_PCIE_L0		0x11 /* L0 state */



/* PEX Internal Configuration Registers */

#define PCIE_STRFMR1		0x71c /* Symbol Timer & Filter Mask Register1 */

#define PCIE_ABSERR		0x8d0 /* Bridge Slave Error Response Register */
@@ -35,20 +30,8 @@ 


#define PCIE_IATU_NUM		6



struct ls_pcie_drvdata {

	u32 lut_offset;

	u32 ltssm_shift;

	u32 lut_dbg;

	const struct dw_pcie_host_ops *ops;

	const struct dw_pcie_ops *dw_pcie_ops;

};



struct ls_pcie {

	struct dw_pcie *pci;

	void __iomem *lut;

	struct regmap *scfg;

	const struct ls_pcie_drvdata *drvdata;

	int index;

};



#define to_ls_pcie(x)	dev_get_drvdata((x)->dev)
@@ -83,38 +66,6 @@ static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie) 
	iowrite32(val, pci->dbi_base + PCIE_STRFMR1);

}



static int ls1021_pcie_link_up(struct dw_pcie *pci)

{

	u32 state;

	struct ls_pcie *pcie = to_ls_pcie(pci);



	if (!pcie->scfg)

		return 0;



	regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state);

	state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;



	if (state < LTSSM_PCIE_L0)

		return 0;



	return 1;

}



static int ls_pcie_link_up(struct dw_pcie *pci)

{

	struct ls_pcie *pcie = to_ls_pcie(pci);

	u32 state;



	state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >>

		 pcie->drvdata->ltssm_shift) &

		 LTSSM_STATE_MASK;



	if (state < LTSSM_PCIE_L0)

		return 0;



	return 1;

}



/* Forward error response of outbound non-posted requests */

static void ls_pcie_fix_error_response(struct ls_pcie *pcie)

{
@@ -139,96 +90,20 @@ static int ls_pcie_host_init(struct pcie_port *pp) 
	return 0;

}



static int ls1021_pcie_host_init(struct pcie_port *pp)

{

	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);

	struct ls_pcie *pcie = to_ls_pcie(pci);

	struct device *dev = pci->dev;

	u32 index[2];

	int ret;



	pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node,

						     "fsl,pcie-scfg");

	if (IS_ERR(pcie->scfg)) {

		ret = PTR_ERR(pcie->scfg);

		dev_err(dev, "No syscfg phandle specified\n");

		pcie->scfg = NULL;

		return ret;

	}



	if (of_property_read_u32_array(dev->of_node,

				       "fsl,pcie-scfg", index, 2)) {

		pcie->scfg = NULL;

		return -EINVAL;

	}

	pcie->index = index[1];



	return ls_pcie_host_init(pp);

}



static const struct dw_pcie_host_ops ls1021_pcie_host_ops = {

	.host_init = ls1021_pcie_host_init,

};



static const struct dw_pcie_host_ops ls_pcie_host_ops = {

	.host_init = ls_pcie_host_init,

};



static const struct dw_pcie_ops dw_ls1021_pcie_ops = {

	.link_up = ls1021_pcie_link_up,

};



static const struct dw_pcie_ops dw_ls_pcie_ops = {

	.link_up = ls_pcie_link_up,

};



static const struct ls_pcie_drvdata ls1021_drvdata = {

	.ops = &ls1021_pcie_host_ops,

	.dw_pcie_ops = &dw_ls1021_pcie_ops,

};



static const struct ls_pcie_drvdata ls1043_drvdata = {

	.lut_offset = 0x10000,

	.ltssm_shift = 24,

	.lut_dbg = 0x7fc,

	.ops = &ls_pcie_host_ops,

	.dw_pcie_ops = &dw_ls_pcie_ops,

};



static const struct ls_pcie_drvdata ls1046_drvdata = {

	.lut_offset = 0x80000,

	.ltssm_shift = 24,

	.lut_dbg = 0x407fc,

	.ops = &ls_pcie_host_ops,

	.dw_pcie_ops = &dw_ls_pcie_ops,

};



static const struct ls_pcie_drvdata ls2080_drvdata = {

	.lut_offset = 0x80000,

	.ltssm_shift = 0,

	.lut_dbg = 0x7fc,

	.ops = &ls_pcie_host_ops,

	.dw_pcie_ops = &dw_ls_pcie_ops,

};



static const struct ls_pcie_drvdata ls2088_drvdata = {

	.lut_offset = 0x80000,

	.ltssm_shift = 0,

	.lut_dbg = 0x407fc,

	.ops = &ls_pcie_host_ops,

	.dw_pcie_ops = &dw_ls_pcie_ops,

};



static const struct of_device_id ls_pcie_of_match[] = {

	{ .compatible = "fsl,ls1012a-pcie", .data = &ls1046_drvdata },

	{ .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },

	{ .compatible = "fsl,ls1028a-pcie", .data = &ls2088_drvdata },

	{ .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },

	{ .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata },

	{ .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata },

	{ .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata },

	{ .compatible = "fsl,ls2088a-pcie", .data = &ls2088_drvdata },

	{ .compatible = "fsl,ls1088a-pcie", .data = &ls2088_drvdata },

	{ .compatible = "fsl,ls1012a-pcie", },

	{ .compatible = "fsl,ls1021a-pcie", },

	{ .compatible = "fsl,ls1028a-pcie", },

	{ .compatible = "fsl,ls1043a-pcie", },

	{ .compatible = "fsl,ls1046a-pcie", },

	{ .compatible = "fsl,ls2080a-pcie", },

	{ .compatible = "fsl,ls2085a-pcie", },

	{ .compatible = "fsl,ls2088a-pcie", },

	{ .compatible = "fsl,ls1088a-pcie", },

	{ },

};
@@ -247,11 +122,8 @@ static int ls_pcie_probe(struct platform_device *pdev) 
	if (!pci)

		return -ENOMEM;



	pcie->drvdata = of_device_get_match_data(dev);



	pci->dev = dev;

	pci->ops = pcie->drvdata->dw_pcie_ops;

	pci->pp.ops = pcie->drvdata->ops;

	pci->pp.ops = &ls_pcie_host_ops;



	pcie->pci = pci;
@@ -260,8 +132,6 @@ static int ls_pcie_probe(struct platform_device *pdev) 
	if (IS_ERR(pci->dbi_base))

		return PTR_ERR(pci->dbi_base);



	pcie->lut = pci->dbi_base + pcie->drvdata->lut_offset;



	if (!ls_pcie_is_bridge(pcie))

		return -ENODEV;

drivers/pci/controller/dwc/pcie-designware.c

+4 −3
Original line number Diff line number Diff line
@@ -672,10 +672,11 @@ void dw_pcie_iatu_detect(struct dw_pcie *pci) 
		if (!pci->atu_base) {

			struct resource *res =

				platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu");

			if (res)

			if (res) {

				pci->atu_size = resource_size(res);

				pci->atu_base = devm_ioremap_resource(dev, res);

			if (IS_ERR(pci->atu_base))

			}

			if (!pci->atu_base || IS_ERR(pci->atu_base))

				pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET;

		}

drivers/pci/controller/dwc/pcie-qcom-ep.c

+1 −3
Original line number Diff line number Diff line
@@ -552,10 +552,8 @@ static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev, 
	int irq, ret;



	irq = platform_get_irq_byname(pdev, "global");

	if (irq < 0) {

		dev_err(&pdev->dev, "Failed to get Global IRQ\n");

	if (irq < 0)

		return irq;

	}



	ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,

					qcom_pcie_ep_global_irq_thread,