Commit 28eb3b36 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge tag 'coresight-next-v5.16.v3' of... 


Merge tag 'coresight-next-v5.16.v3' of gitolite.kernel.org:pub/scm/linux/kernel/git/coresight/linux into char-misc-next

Mathieu writes:

Coresight changes for v5.16

- A new option to make coresight cpu-debug capabilities available as early
as possible in the kernel boot process.

- Make trace sessions more enduring by coping with scenarios where events
are scheduled on CPUs that can't reach the selected sink.

- A set of improvement to make the TMC-ETR driver more efficient.

- Enhancements to the TRBE driver to correct several errata.

- An enhancement to make the AXI burts size configurable for TMC devices
that can't work with the default value.

- A fix in the CTI module to use the correct device when calling
pm_runtime_put()

- The addition of the Kryo-5xx device to the list of support ETMs.

Signed-off-by: default avatarMathieu Poirier <mathieu.poirier@linaro.org>

* tag 'coresight-next-v5.16.v3' of gitolite.kernel.org:pub/scm/linux/kernel/git/coresight/linux: (39 commits)
  arm64: errata: Enable TRBE workaround for write to out-of-range address
  arm64: errata: Enable workaround for TRBE overwrite in FILL mode
  coresight: trbe: Work around write to out of range
  coresight: trbe: Make sure we have enough space
  coresight: trbe: Add a helper to determine the minimum buffer size
  coresight: trbe: Workaround TRBE errata overwrite in FILL mode
  coresight: trbe: Add infrastructure for Errata handling
  coresight: trbe: Allow driver to choose a different alignment
  coresight: trbe: Decouple buffer base from the hardware base
  coresight: trbe: Add a helper to pad a given buffer area
  coresight: trbe: Add a helper to calculate the trace generated
  coresight: trbe: Defer the probe on offline CPUs
  coresight: trbe: Fix incorrect access of the sink specific data
  coresight: etm4x: Add ETM PID for Kryo-5XX
  coresight: trbe: Prohibit trace before disabling TRBE
  coresight: trbe: End the AUX handle on truncation
  coresight: trbe: Do not truncate buffer on IRQ
  coresight: trbe: Fix handling of spurious interrupts
  coresight: trbe: irq handler: Do not disable TRBE if no action is needed
  coresight: trbe: Unify the enabling sequence
  ...
parents 27182be9 561ced0b

Documentation/arm64/silicon-errata.rst

+12 −0
Original line number Diff line number Diff line
@@ -92,12 +92,24 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A77      | #1508412        | ARM64_ERRATUM_1508412       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A710     | #2119858        | ARM64_ERRATUM_2119858       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A710     | #2054223        | ARM64_ERRATUM_2054223       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A710     | #2224489        | ARM64_ERRATUM_2224489       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N1     | #1188873,1418040| ARM64_ERRATUM_1418040       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N1     | #1349291        | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N1     | #1542419        | ARM64_ERRATUM_1542419       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N2     | #2139208        | ARM64_ERRATUM_2139208       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N2     | #2067961        | ARM64_ERRATUM_2067961       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N2     | #2253138        | ARM64_ERRATUM_2253138       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | MMU-500         | #841119,826419  | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

+----------------+-----------------+-----------------+-----------------------------+

Documentation/devicetree/bindings/arm/coresight.txt

+5 −0
Original line number Diff line number Diff line
@@ -127,6 +127,11 @@ its hardware characteristcs. 
	* arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely

	  use the SG mode on this system.



	* arm,max-burst-size: The maximum burst size initiated by TMC on the

	  AXI master interface. The burst size can be in the range [0..15],

	  the setting supports one data transfer per burst up to a maximum of

	  16 data transfers per burst.



* Optional property for CATU :

	* interrupts : Exactly one SPI may be listed for reporting the address

	  error

arch/arm64/Kconfig

+111 −0
Original line number Diff line number Diff line
@@ -666,6 +666,117 @@ config ARM64_ERRATUM_1508412 


	  If unsure, say Y.



config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE

	bool



config ARM64_ERRATUM_2119858

	bool "Cortex-A710: 2119858: workaround TRBE overwriting trace data in FILL mode"

	default y

	depends on CORESIGHT_TRBE

	select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE

	help

	  This option adds the workaround for ARM Cortex-A710 erratum 2119858.



	  Affected Cortex-A710 cores could overwrite up to 3 cache lines of trace

	  data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in

	  the event of a WRAP event.



	  Work around the issue by always making sure we move the TRBPTR_EL1 by

	  256 bytes before enabling the buffer and filling the first 256 bytes of

	  the buffer with ETM ignore packets upon disabling.



	  If unsure, say Y.



config ARM64_ERRATUM_2139208

	bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"

	default y

	depends on CORESIGHT_TRBE

	select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE

	help

	  This option adds the workaround for ARM Neoverse-N2 erratum 2139208.



	  Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace

	  data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in

	  the event of a WRAP event.



	  Work around the issue by always making sure we move the TRBPTR_EL1 by

	  256 bytes before enabling the buffer and filling the first 256 bytes of

	  the buffer with ETM ignore packets upon disabling.



	  If unsure, say Y.



config ARM64_WORKAROUND_TSB_FLUSH_FAILURE

	bool



config ARM64_ERRATUM_2054223

	bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"

	default y

	select ARM64_WORKAROUND_TSB_FLUSH_FAILURE

	help

	  Enable workaround for ARM Cortex-A710 erratum 2054223



	  Affected cores may fail to flush the trace data on a TSB instruction, when

	  the PE is in trace prohibited state. This will cause losing a few bytes

	  of the trace cached.



	  Workaround is to issue two TSB consecutively on affected cores.



	  If unsure, say Y.



config ARM64_ERRATUM_2067961

	bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"

	default y

	select ARM64_WORKAROUND_TSB_FLUSH_FAILURE

	help

	  Enable workaround for ARM Neoverse-N2 erratum 2067961



	  Affected cores may fail to flush the trace data on a TSB instruction, when

	  the PE is in trace prohibited state. This will cause losing a few bytes

	  of the trace cached.



	  Workaround is to issue two TSB consecutively on affected cores.



	  If unsure, say Y.



config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE

	bool



config ARM64_ERRATUM_2253138

	bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"

	depends on CORESIGHT_TRBE

	default y

	select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE

	help

	  This option adds the workaround for ARM Neoverse-N2 erratum 2253138.



	  Affected Neoverse-N2 cores might write to an out-of-range address, not reserved

	  for TRBE. Under some conditions, the TRBE might generate a write to the next

	  virtually addressed page following the last page of the TRBE address space

	  (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.



	  Work around this in the driver by always making sure that there is a

	  page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.



	  If unsure, say Y.



config ARM64_ERRATUM_2224489

	bool "Cortex-A710: 2224489: workaround TRBE writing to address out-of-range"

	depends on CORESIGHT_TRBE

	default y

	select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE

	help

	  This option adds the workaround for ARM Cortex-A710 erratum 2224489.



	  Affected Cortex-A710 cores might write to an out-of-range address, not reserved

	  for TRBE. Under some conditions, the TRBE might generate a write to the next

	  virtually addressed page following the last page of the TRBE address space

	  (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.



	  Work around this in the driver by always making sure that there is a

	  page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.



	  If unsure, say Y.



config CAVIUM_ERRATUM_22375

	bool "Cavium erratum 22375, 24313"

	default y

arch/arm64/include/asm/barrier.h

+15 −1
Original line number Diff line number Diff line
@@ -23,7 +23,7 @@ 
#define dsb(opt)	asm volatile("dsb " #opt : : : "memory")



#define psb_csync()	asm volatile("hint #17" : : : "memory")

#define tsb_csync()	asm volatile("hint #18" : : : "memory")

#define __tsb_csync()	asm volatile("hint #18" : : : "memory")

#define csdb()		asm volatile("hint #20" : : : "memory")



#ifdef CONFIG_ARM64_PSEUDO_NMI
@@ -46,6 +46,20 @@ 
#define dma_rmb()	dmb(oshld)

#define dma_wmb()	dmb(oshst)





#define tsb_csync()								\

	do {									\

		/*								\

		 * CPUs affected by Arm Erratum 2054223 or 2067961 needs	\

		 * another TSB to ensure the trace is flushed. The barriers	\

		 * don't have to be strictly back to back, as long as the	\

		 * CPU is in trace prohibited state.				\

		 */								\

		if (cpus_have_final_cap(ARM64_WORKAROUND_TSB_FLUSH_FAILURE))	\

			__tsb_csync();						\

		__tsb_csync();							\

	} while (0)



/*

 * Generate a mask for array_index__nospec() that is ~0UL when 0 <= idx < sz

 * and 0 otherwise.

arch/arm64/include/asm/cputype.h

+4 −0
Original line number Diff line number Diff line
@@ -73,6 +73,8 @@ 
#define ARM_CPU_PART_CORTEX_A76		0xD0B

#define ARM_CPU_PART_NEOVERSE_N1	0xD0C

#define ARM_CPU_PART_CORTEX_A77		0xD0D

#define ARM_CPU_PART_CORTEX_A710	0xD47

#define ARM_CPU_PART_NEOVERSE_N2	0xD49



#define APM_CPU_PART_POTENZA		0x000
@@ -113,6 +115,8 @@ 
#define MIDR_CORTEX_A76	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)

#define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)

#define MIDR_CORTEX_A77	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77)

#define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710)

#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)

#define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)

#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)

#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)