Commit 28dee8ef authored by Manikanta Pubbisetty's avatar Manikanta Pubbisetty Committed by Kalle Valo
Browse files

ath11k: fix vht guard interval mapping 



Guard interval value which comes from VHT_SIG_A TLV has a mapping
where value 0 corresponds to LGI, 1 and 3 corresponds to SGI.

Value 3 which is SGI(0.4us) in VHT was incorrectly mapped to a GI
of 3.2us(only applicable in HE) resulting in incorrect rx GI stats.
Fixing the mapping.

Signed-off-by: default avatarManikanta Pubbisetty <mpubbise@codeaurora.org>
Signed-off-by: default avatarKalle Valo <kvalo@codeaurora.org>
parent 5e02bc73

drivers/net/wireless/ath/ath11k/hal_rx.c

+13 −3
Original line number Diff line number Diff line
@@ -920,6 +920,7 @@ ath11k_hal_rx_parse_mon_status_tlv(struct ath11k_base *ab, 
			(struct hal_rx_vht_sig_a_info *)tlv_data;

		u32 nsts;

		u32 group_id;

		u8 gi_setting;



		info0 = __le32_to_cpu(vht_sig->info0);

		info1 = __le32_to_cpu(vht_sig->info1);
@@ -928,9 +929,18 @@ ath11k_hal_rx_parse_mon_status_tlv(struct ath11k_base *ab, 
					    info0);

		ppdu_info->mcs = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO1_MCS,

					   info1);

		ppdu_info->gi =

			FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING,

		gi_setting = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING,

				       info1);

		switch (gi_setting) {

		case HAL_RX_VHT_SIG_A_NORMAL_GI:

			ppdu_info->gi = HAL_RX_GI_0_8_US;

			break;

		case HAL_RX_VHT_SIG_A_SHORT_GI:

		case HAL_RX_VHT_SIG_A_SHORT_GI_AMBIGUITY:

			ppdu_info->gi = HAL_RX_GI_0_4_US;

			break;

		}



		ppdu_info->is_stbc = info0 & HAL_RX_VHT_SIG_A_INFO_INFO0_STBC;

		nsts = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS, info0);

		if (ppdu_info->is_stbc && nsts > 0)

drivers/net/wireless/ath/ath11k/hal_rx.h

+6 −0
Original line number Diff line number Diff line
@@ -189,6 +189,12 @@ struct hal_rx_vht_sig_a_info { 
	__le32 info1;

} __packed;



enum hal_rx_vht_sig_a_gi_setting {

	HAL_RX_VHT_SIG_A_NORMAL_GI = 0,

	HAL_RX_VHT_SIG_A_SHORT_GI = 1,

	HAL_RX_VHT_SIG_A_SHORT_GI_AMBIGUITY = 3,

};



#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS	GENMASK(6, 3)

#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM		BIT(7)

#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW	GENMASK(20, 19)