Unverified Commit 28b2cacc authored Apr 25, 2024 by openeuler-ci-bot Committed by Gitee Apr 25, 2024

!6616 drm/amdgpu: Reset IH OVERFLOW_CLEAR bit

Merge Pull Request from: @ci-robot 
 
PR sync from: Liu Chuang <liuchuang40@huawei.com>
https://mailweb.openeuler.org/hyperkitty/list/kernel@openeuler.org/message/DJ427QS4PNMDJYB3JKPVJE3MLV22LI7Y/ 
 
https://gitee.com/src-openeuler/kernel/issues/I9HL6R 
 
Link:https://gitee.com/openeuler/kernel/pulls/6616

 

Reviewed-by: Liu YongQiang <liuyongqiang13@huawei.com>
Signed-off-by: Zhang Changzhong <zhangchangzhong@huawei.com>

parents fa3f9ee5 ff613de9

drivers/gpu/drm/amd/amdgpu/cik_ih.c

+6 −0

Original line number	Diff line number	Diff line
		@@ -201,6 +201,12 @@ static u32 cik_ih_get_wptr(struct amdgpu_device *adev)
		tmp = RREG32(mmIH_RB_CNTL);
		tmp \|= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
		WREG32(mmIH_RB_CNTL, tmp);

		/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
		* can be detected.
		*/
		tmp &= ~IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
		WREG32(mmIH_RB_CNTL, tmp);
		}
		return (wptr & adev->irq.ih.ptr_mask);
		}

drivers/gpu/drm/amd/amdgpu/cz_ih.c

+6 −0

Original line number	Diff line number	Diff line
		@@ -203,6 +203,12 @@ static u32 cz_ih_get_wptr(struct amdgpu_device *adev)
		tmp = RREG32(mmIH_RB_CNTL);
		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
		WREG32(mmIH_RB_CNTL, tmp);

		/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
		* can be detected.
		*/
		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
		WREG32(mmIH_RB_CNTL, tmp);
		}
		return (wptr & adev->irq.ih.ptr_mask);
		}

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

+6 −0

Original line number	Diff line number	Diff line
		@@ -203,6 +203,12 @@ static u32 iceland_ih_get_wptr(struct amdgpu_device *adev)
		tmp = RREG32(mmIH_RB_CNTL);
		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
		WREG32(mmIH_RB_CNTL, tmp);

		/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
		* can be detected.
		*/
		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
		WREG32(mmIH_RB_CNTL, tmp);
		}
		return (wptr & adev->irq.ih.ptr_mask);
		}

drivers/gpu/drm/amd/amdgpu/si_ih.c

+6 −0

Original line number	Diff line number	Diff line
		@@ -115,6 +115,12 @@ static u32 si_ih_get_wptr(struct amdgpu_device *adev)
		tmp = RREG32(IH_RB_CNTL);
		tmp \|= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
		WREG32(IH_RB_CNTL, tmp);

		/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
		* can be detected.
		*/
		tmp &= ~IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
		WREG32(IH_RB_CNTL, tmp);
		}
		return (wptr & adev->irq.ih.ptr_mask);
		}

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

+6 −0

Original line number	Diff line number	Diff line
		@@ -214,6 +214,12 @@ static u32 tonga_ih_get_wptr(struct amdgpu_device *adev)
		tmp = RREG32(mmIH_RB_CNTL);
		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
		WREG32(mmIH_RB_CNTL, tmp);

		/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
		* can be detected.
		*/
		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
		WREG32(mmIH_RB_CNTL, tmp);
		}
		return (wptr & adev->irq.ih.ptr_mask);
		}