Commit 28a1f789 authored by Tvrtko Ursulin's avatar Tvrtko Ursulin
Browse files

drm/i915: Consolidate some open coded mmio rmw 



Replace some gen6/7 open coded rmw with intel_uncore_rmw.

Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190621070811.7006-14-tvrtko.ursulin@linux.intel.com
parent acb56d97

drivers/gpu/drm/i915/i915_gem_gtt.c

+18 −23
Original line number Original line Diff line number Diff line
@@ -1725,13 +1725,10 @@ static void gen7_ppgtt_enable(struct intel_gt *gt) 
	struct drm_i915_private *i915 = gt->i915;

	struct drm_i915_private *i915 = gt->i915;

	struct intel_uncore *uncore = gt->uncore;

	struct intel_uncore *uncore = gt->uncore;

	struct intel_engine_cs *engine;

	struct intel_engine_cs *engine;

	u32 ecochk, ecobits;

	enum intel_engine_id id;

	enum intel_engine_id id;

	u32 ecochk;





	ecobits = intel_uncore_read(uncore, GAC_ECO_BITS);

	intel_uncore_rmw(uncore, GAC_ECO_BITS, 0, ECOBITS_PPGTT_CACHE64B);

	intel_uncore_write(uncore,

			   GAC_ECO_BITS,

			   ecobits | ECOBITS_PPGTT_CACHE64B);





	ecochk = intel_uncore_read(uncore, GAM_ECOCHK);

	ecochk = intel_uncore_read(uncore, GAM_ECOCHK);

	if (IS_HASWELL(i915)) {

	if (IS_HASWELL(i915)) {
@@ -1753,22 +1750,21 @@ static void gen7_ppgtt_enable(struct intel_gt *gt) 
static void gen6_ppgtt_enable(struct intel_gt *gt)

static void gen6_ppgtt_enable(struct intel_gt *gt)

{

{

	struct intel_uncore *uncore = gt->uncore;

	struct intel_uncore *uncore = gt->uncore;

	u32 ecochk, gab_ctl, ecobits;





	ecobits = intel_uncore_read(uncore, GAC_ECO_BITS);

	intel_uncore_rmw(uncore,

	intel_uncore_write(uncore,

			 GAC_ECO_BITS,

			 GAC_ECO_BITS,

			   ecobits | ECOBITS_SNB_BIT | ECOBITS_PPGTT_CACHE64B);

			 0,

			 ECOBITS_SNB_BIT | ECOBITS_PPGTT_CACHE64B);





	gab_ctl = intel_uncore_read(uncore, GAB_CTL);

	intel_uncore_rmw(uncore,

	intel_uncore_write(uncore,

			 GAB_CTL,

			 GAB_CTL,

			   gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);

			 0,

			 GAB_CTL_CONT_AFTER_PAGEFAULT);





	ecochk = intel_uncore_read(uncore, GAM_ECOCHK);

	intel_uncore_rmw(uncore,

	intel_uncore_write(uncore,

			 GAM_ECOCHK,

			 GAM_ECOCHK,

			   ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);

			 0,

			 ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);





	if (HAS_PPGTT(uncore->i915)) /* may be disabled for VT-d */

	if (HAS_PPGTT(uncore->i915)) /* may be disabled for VT-d */

		intel_uncore_write(uncore,

		intel_uncore_write(uncore,
@@ -2226,10 +2222,9 @@ static void gtt_write_workarounds(struct intel_gt *gt) 
	 */

	 */

	if (HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_64K) &&

	if (HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_64K) &&

	    INTEL_GEN(i915) <= 10)

	    INTEL_GEN(i915) <= 10)

		intel_uncore_write(uncore,

		intel_uncore_rmw(uncore,

				 GEN8_GAMW_ECO_DEV_RW_IA,

				 GEN8_GAMW_ECO_DEV_RW_IA,

				   intel_uncore_read(uncore,

				 0,

						     GEN8_GAMW_ECO_DEV_RW_IA) |

				 GAMW_ECO_ENABLE_64K_IPS_FIELD);

				 GAMW_ECO_ENABLE_64K_IPS_FIELD);

}

}