Commit 289037d6 authored by Weilong Chen's avatar Weilong Chen Committed by Yang Yingliang
Browse files

cache: Workaround HiSilicon Taishan DC CVAU 



ascend inclusion
category: feature
bugzilla: 46922
CVE: NA

-------------------------------------

Taishan's L1/L2 cache is inclusive, and the data is consistent.
Any change of L1 does not require DC operation to brush CL in L1 to L2.
It's safe that don't clean data cache by address to point of unification.

Without IDC featrue, kernel needs to flush icache as well as dcache,
causes performance degradation.

The flaw refers to V110/V200 variant 1.

Reviewed-by: default avatarKefeng Wang <wangkefeng.wang@huawei.com>
Reviewed-by: default avatarDing Tianhong <dingtianhong@huawei.com>
Signed-off-by: default avatarYang Yingliang <yangyingliang@huawei.com>
Signed-off-by: default avatarWeilong Chen <chenweilong@huawei.com>
Reviewed-by: default avatarKefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: default avatarYang Yingliang <yangyingliang@huawei.com>
parent 5b22bdbb

Documentation/arm64/silicon-errata.txt

+1 −0
Original line number Diff line number Diff line
@@ -75,6 +75,7 @@ stable kernels. 
| Hisilicon      | Hip0{5,6,7}     | #161010101      | HISILICON_ERRATUM_161010101 |

| Hisilicon      | Hip0{6,7}       | #161010701      | N/A                         |

| Hisilicon      | Hip07           | #161600802      | HISILICON_ERRATUM_161600802 |

| Hisilicon      | TSV{110,200}    | #1980005        | HISILICON_ERRATUM_1980005   |

|                |                 |                 |                             |

| Qualcomm Tech. | Kryo/Falkor v1  | E1003           | QCOM_FALKOR_ERRATUM_1003    |

| Qualcomm Tech. | Falkor v1       | E1009           | QCOM_FALKOR_ERRATUM_1009    |

arch/arm64/Kconfig

+9 −0
Original line number Diff line number Diff line
@@ -619,6 +619,15 @@ config HISILICON_ERRATUM_161600802 


	  If unsure, say Y.



config HISILICON_ERRATUM_1980005

	bool "Hisilicon erratum IDC support"

	default n

	help

	  The HiSilicon TSV100/200 SoC support idc but report wrong value to

	  kernel.



	  If unsure, say N.



config QCOM_FALKOR_ERRATUM_E1041

	bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"

	default y

arch/arm64/include/asm/cpucaps.h

+2 −1
Original line number Diff line number Diff line
@@ -56,7 +56,8 @@ 
#define ARM64_WORKAROUND_1463225		35

#define ARM64_HAS_CRC32				36

#define ARM64_SSBS				37

#define ARM64_WORKAROUND_HISILICON_1980005	38



#define ARM64_NCAPS				38

#define ARM64_NCAPS				39



#endif /* __ASM_CPUCAPS_H */

arch/arm64/include/asm/cputype.h

+2 −0
Original line number Diff line number Diff line
@@ -155,6 +155,8 @@ struct midr_range { 
		.rv_max = MIDR_CPU_VAR_REV(v_max, r_max),	\

	}



#define MIDR_REV_RANGE(m, v, r_min, r_max) MIDR_RANGE(m, v, r_min, v, r_max)

#define MIDR_REV(m, v, r) MIDR_RANGE(m, v, r, v, r)

#define MIDR_ALL_VERSIONS(m) MIDR_RANGE(m, 0, 0, 0xf, 0xf)



static inline bool midr_is_cpu_model_range(u32 midr, u32 model, u32 rv_min,

arch/arm64/kernel/cpu_errata.c

+32 −0
Original line number Diff line number Diff line
@@ -71,6 +71,29 @@ is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope) 
	return model == entry->midr_range.model;

}



#ifdef CONFIG_HISILICON_ERRATUM_1980005

static bool

hisilicon_1980005_match(const struct arm64_cpu_capabilities *entry,

		int scope)

{

	static const struct midr_range idc_support_list[] = {

		MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),

		MIDR_REV(MIDR_HISI_TSV200, 1, 0),

		{ /* sentinel */ }

	};



	return  is_midr_in_range_list(read_cpuid_id(), idc_support_list);

}



static void

hisilicon_1980005_enable(const struct arm64_cpu_capabilities *__unused)

{

	cpus_set_cap(ARM64_HAS_CACHE_IDC);

	arm64_ftr_reg_ctrel0.sys_val |= BIT(CTR_IDC_SHIFT);

	sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);

}

#endif



static bool

has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry,

			  int scope)
@@ -848,6 +871,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,

		.cpu_enable = cpu_enable_trap_ctr_access,

	},

#ifdef CONFIG_HISILICON_ERRATUM_1980005

	{

		.desc = "Taishan IDC coherence workaround",

		.capability = ARM64_WORKAROUND_HISILICON_1980005,

		.matches = hisilicon_1980005_match,

		.type = ARM64_CPUCAP_SYSTEM_FEATURE,

		.cpu_enable = hisilicon_1980005_enable,

	},

#endif

#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003

	{

		.desc = "Qualcomm Technologies Falkor erratum 1003",