Commit 287f037d authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'x86_cache_for_6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 cache resource control updates from Dave Hansen:
 "These declare the resource control (rectrl) MSRs a bit more normally
  and clean up an unnecessary structure member:

   - Remove unnecessary arch_has_empty_bitmaps structure memory

   - Move rescrtl MSR defines into msr-index.h, like normal MSRs"

* tag 'x86_cache_for_6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/resctrl: Move MSR defines into msr-index.h
  x86/resctrl: Remove arch_has_empty_bitmaps
parents a89ef2aa 97fa21f6

arch/x86/include/asm/msr-index.h

+15 −6
Original line number Diff line number Diff line
@@ -4,12 +4,7 @@ 


#include <linux/bits.h>



/*

 * CPU model specific register (MSR) numbers.

 *

 * Do not add new entries to this file unless the definitions are shared

 * between multiple compilation units.

 */

/* CPU model specific register (MSR) numbers. */



/* x86-64 specific MSRs */

#define MSR_EFER		0xc0000080 /* extended feature register */
@@ -1052,6 +1047,20 @@ 
#define VMX_BASIC_MEM_TYPE_WB	6LLU

#define VMX_BASIC_INOUT		0x0040000000000000LLU



/* Resctrl MSRs: */

/* - Intel: */

#define MSR_IA32_L3_QOS_CFG		0xc81

#define MSR_IA32_L2_QOS_CFG		0xc82

#define MSR_IA32_QM_EVTSEL		0xc8d

#define MSR_IA32_QM_CTR			0xc8e

#define MSR_IA32_PQR_ASSOC		0xc8f

#define MSR_IA32_L3_CBM_BASE		0xc90

#define MSR_IA32_L2_CBM_BASE		0xd10

#define MSR_IA32_MBA_THRTL_BASE		0xd50



/* - AMD: */

#define MSR_IA32_MBA_BW_BASE		0xc0000200



/* MSR_IA32_VMX_MISC bits */

#define MSR_IA32_VMX_MISC_INTEL_PT                 (1ULL << 14)

#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)

arch/x86/include/asm/resctrl.h

+3 −5
Original line number Diff line number Diff line
@@ -7,8 +7,6 @@ 
#include <linux/sched.h>

#include <linux/jump_label.h>



#define IA32_PQR_ASSOC	0x0c8f



/**

 * struct resctrl_pqr_state - State cache for the PQR MSR

 * @cur_rmid:		The cached Resource Monitoring ID
@@ -16,8 +14,8 @@ 
 * @default_rmid:	The user assigned Resource Monitoring ID

 * @default_closid:	The user assigned cached Class Of Service ID

 *

 * The upper 32 bits of IA32_PQR_ASSOC contain closid and the

 * lower 10 bits rmid. The update to IA32_PQR_ASSOC always

 * The upper 32 bits of MSR_IA32_PQR_ASSOC contain closid and the

 * lower 10 bits rmid. The update to MSR_IA32_PQR_ASSOC always

 * contains both parts, so we need to cache them. This also

 * stores the user configured per cpu CLOSID and RMID.

 *
@@ -77,7 +75,7 @@ static void __resctrl_sched_in(void) 
	if (closid != state->cur_closid || rmid != state->cur_rmid) {

		state->cur_closid = closid;

		state->cur_rmid = rmid;

		wrmsr(IA32_PQR_ASSOC, rmid, closid);

		wrmsr(MSR_IA32_PQR_ASSOC, rmid, closid);

	}

}

arch/x86/kernel/cpu/resctrl/core.c

+1 −3
Original line number Diff line number Diff line
@@ -575,7 +575,7 @@ static void clear_closid_rmid(int cpu) 
	state->default_rmid = 0;

	state->cur_closid = 0;

	state->cur_rmid = 0;

	wrmsr(IA32_PQR_ASSOC, 0, 0);

	wrmsr(MSR_IA32_PQR_ASSOC, 0, 0);

}



static int resctrl_online_cpu(unsigned int cpu)
@@ -828,7 +828,6 @@ static __init void rdt_init_res_defs_intel(void) 
		if (r->rid == RDT_RESOURCE_L3 ||

		    r->rid == RDT_RESOURCE_L2) {

			r->cache.arch_has_sparse_bitmaps = false;

			r->cache.arch_has_empty_bitmaps = false;

			r->cache.arch_has_per_cpu_cfg = false;

			r->cache.min_cbm_bits = 1;

		} else if (r->rid == RDT_RESOURCE_MBA) {
@@ -849,7 +848,6 @@ static __init void rdt_init_res_defs_amd(void) 
		if (r->rid == RDT_RESOURCE_L3 ||

		    r->rid == RDT_RESOURCE_L2) {

			r->cache.arch_has_sparse_bitmaps = true;

			r->cache.arch_has_empty_bitmaps = true;

			r->cache.arch_has_per_cpu_cfg = true;

			r->cache.min_cbm_bits = 0;

		} else if (r->rid == RDT_RESOURCE_MBA) {

arch/x86/kernel/cpu/resctrl/ctrlmondata.c

+1 −2
Original line number Diff line number Diff line
@@ -105,8 +105,7 @@ static bool cbm_validate(char *buf, u32 *data, struct rdt_resource *r) 
		return false;

	}



	if ((!r->cache.arch_has_empty_bitmaps && val == 0) ||

	    val > r->default_ctrl) {

	if ((r->cache.min_cbm_bits > 0 && val == 0) || val > r->default_ctrl) {

		rdt_last_cmd_puts("Mask out of range\n");

		return false;

	}

arch/x86/kernel/cpu/resctrl/internal.h

+0 −10
Original line number Diff line number Diff line
@@ -8,16 +8,6 @@ 
#include <linux/fs_context.h>

#include <linux/jump_label.h>



#define MSR_IA32_L3_QOS_CFG		0xc81

#define MSR_IA32_L2_QOS_CFG		0xc82

#define MSR_IA32_L3_CBM_BASE		0xc90

#define MSR_IA32_L2_CBM_BASE		0xd10

#define MSR_IA32_MBA_THRTL_BASE		0xd50

#define MSR_IA32_MBA_BW_BASE		0xc0000200



#define MSR_IA32_QM_CTR			0x0c8e

#define MSR_IA32_QM_EVTSEL		0x0c8d



#define L3_QOS_CDP_ENABLE		0x01ULL



#define L2_QOS_CDP_ENABLE		0x01ULL