Commit 28449820 authored by Rodrigo Siqueira's avatar Rodrigo Siqueira Committed by Alex Deucher
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drm/amd/display: Reduce frame size in the bouding box for DCN31/316 



GCC throw warnings for the function dcn31_update_bw_bounding_box and
dcn316_update_bw_bounding_box due to its frame size that looks like
this:

 error: the frame size of 1936 bytes is larger than 1024 bytes [-Werror=frame-larger-than=]

For fixing this issue I dropped an intermadiate variable.

Cc: Stephen Rothwell <sfr@canb.auug.org.au>
Cc: Hamza Mahfooz <hamza.mahfooz@amd.com>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Reviewed-by: default avatarHarry Wentland <harry.wentland@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 87d6b28e

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

+26 −32
Original line number Diff line number Diff line
@@ -575,7 +575,6 @@ void dcn31_calculate_wm_and_dlg_fp( 
void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

{

	struct clk_limit_table *clk_table = &bw_params->clk_table;

	struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];

	unsigned int i, closest_clk_lvl;

	int j;
@@ -608,29 +607,27 @@ void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params 
				}

			}



			clock_limits[i].state = i;

			dcn3_1_soc.clock_limits[i].state = i;



			/* Clocks dependent on voltage level. */

			clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;

			clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;

			clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;

			clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;

			dcn3_1_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;

			dcn3_1_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;

			dcn3_1_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;

			dcn3_1_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;



			/* Clocks independent of voltage level. */

			clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :

			dcn3_1_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :

				dcn3_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;



			clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :

			dcn3_1_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :

				dcn3_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;



			clock_limits[i].dram_bw_per_chan_gbps = dcn3_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;

			clock_limits[i].dscclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;

			clock_limits[i].dtbclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;

			clock_limits[i].phyclk_d18_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;

			clock_limits[i].phyclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;

			dcn3_1_soc.clock_limits[i].dram_bw_per_chan_gbps = dcn3_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;

			dcn3_1_soc.clock_limits[i].dscclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;

			dcn3_1_soc.clock_limits[i].dtbclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;

			dcn3_1_soc.clock_limits[i].phyclk_d18_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;

			dcn3_1_soc.clock_limits[i].phyclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;

		}

		for (i = 0; i < clk_table->num_entries; i++)

			dcn3_1_soc.clock_limits[i] = clock_limits[i];

		if (clk_table->num_entries) {

			dcn3_1_soc.num_states = clk_table->num_entries;

		}
@@ -702,7 +699,6 @@ void dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param 
void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

{

	struct clk_limit_table *clk_table = &bw_params->clk_table;

	struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];

	unsigned int i, closest_clk_lvl;

	int max_dispclk_mhz = 0, max_dppclk_mhz = 0;

	int j;
@@ -740,34 +736,32 @@ void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param 
				closest_clk_lvl = dcn3_16_soc.num_states - 1;

			}



			clock_limits[i].state = i;

			dcn3_16_soc.clock_limits[i].state = i;



			/* Clocks dependent on voltage level. */

			clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;

			dcn3_16_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;

			if (clk_table->num_entries == 1 &&

				clock_limits[i].dcfclk_mhz < dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) {

				dcn3_16_soc.clock_limits[i].dcfclk_mhz < dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) {

				/*SMU fix not released yet*/

				clock_limits[i].dcfclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz;

				dcn3_16_soc.clock_limits[i].dcfclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz;

			}

			clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;

			clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;

			clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;

			dcn3_16_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;

			dcn3_16_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;

			dcn3_16_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;



			/* Clocks independent of voltage level. */

			clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :

			dcn3_16_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :

				dcn3_16_soc.clock_limits[closest_clk_lvl].dispclk_mhz;



			clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :

			dcn3_16_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :

				dcn3_16_soc.clock_limits[closest_clk_lvl].dppclk_mhz;



			clock_limits[i].dram_bw_per_chan_gbps = dcn3_16_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;

			clock_limits[i].dscclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dscclk_mhz;

			clock_limits[i].dtbclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;

			clock_limits[i].phyclk_d18_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;

			clock_limits[i].phyclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_mhz;

			dcn3_16_soc.clock_limits[i].dram_bw_per_chan_gbps = dcn3_16_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;

			dcn3_16_soc.clock_limits[i].dscclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dscclk_mhz;

			dcn3_16_soc.clock_limits[i].dtbclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;

			dcn3_16_soc.clock_limits[i].phyclk_d18_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;

			dcn3_16_soc.clock_limits[i].phyclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_mhz;

		}

		for (i = 0; i < clk_table->num_entries; i++)

			dcn3_16_soc.clock_limits[i] = clock_limits[i];

		if (clk_table->num_entries) {

			dcn3_16_soc.num_states = clk_table->num_entries;

		}