Commit 2838cfdd authored by Thierry Reding's avatar Thierry Reding
Browse files

arm64: tegra: Bump #address-cells and #size-cells 



The #address-cells and #size-cells properties for the top-level bus were
set to 1 because that was enough to represent the register ranges of all
the IP blocks on that bus. However, most of these devices can do DMA to
a larger address space, so translation of DMA addresses needs to happen
in a 64-bit address space.

Partially this was already done by the memory controller increasing that
address space by setting #address-cells and #size-cells to 2, but a full
DMA address translation would still cause truncation when traversing to
the top-level bus.

Fix this by setting #address-cells = <2> and #size-cells = <2> on the
top-level bus and adjusting all "reg" and "ranges" properties of its
children.

While at it, also move the PCI and GPU nodes back under the top-level
bus where they belong. The were put outside of it to work around this
same problem.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent c71e1897

arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts

+42 −42
Original line number Diff line number Diff line
@@ -2184,7 +2184,6 @@ 
							 GPIO_ACTIVE_LOW>;

			};

		};

	};



		pcie@14100000 {

			status = "okay";
@@ -2246,6 +2245,7 @@ 
			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",

				    "p2u-5", "p2u-6", "p2u-7";

		};

	};



	fan: pwm-fan {

		compatible = "pwm-fan";

arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi

+27 −27
Original line number Diff line number Diff line
@@ -2209,7 +2209,6 @@ 
							 GPIO_ACTIVE_LOW>;

			};

		};

	};



		pcie@14160000 {

			status = "okay";
@@ -2250,6 +2249,7 @@ 
			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",

				    "p2u-5", "p2u-6", "p2u-7";

		};

	};



	fan: pwm-fan {

		compatible = "pwm-fan";

arch/arm64/boot/dts/nvidia/tegra194.dtsi

+566 −562

File changed.

Preview size limit exceeded, changes collapsed.

arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts

+51 −51
Original line number Diff line number Diff line
@@ -2048,6 +2048,57 @@ 
				};

			};

		};



		pcie@14100000 {

			status = "okay";



			vddio-pex-ctl-supply = <&vdd_1v8_ao>;



			phys = <&p2u_hsio_3>;

			phy-names = "p2u-0";

		};



		pcie@14160000 {

			status = "okay";



			vddio-pex-ctl-supply = <&vdd_1v8_ao>;



			phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,

			       <&p2u_hsio_7>;

			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";

		};



		pcie@141a0000 {

			status = "okay";



			vddio-pex-ctl-supply = <&vdd_1v8_ls>;

			vpcie3v3-supply = <&vdd_3v3_pcie>;

			vpcie12v-supply = <&vdd_12v_pcie>;



			phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,

			       <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,

			       <&p2u_nvhs_6>, <&p2u_nvhs_7>;

			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",

				    "p2u-5", "p2u-6", "p2u-7";

		};



		pcie-ep@141a0000 {

			status = "disabled";



			vddio-pex-ctl-supply = <&vdd_1v8_ls>;



			reset-gpios = <&gpio TEGRA234_MAIN_GPIO(AF, 1) GPIO_ACTIVE_LOW>;



			nvidia,refclk-select-gpios = <&gpio_aon

						      TEGRA234_AON_GPIO(AA, 4)

						      GPIO_ACTIVE_HIGH>;



			phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,

			       <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,

			       <&p2u_nvhs_6>, <&p2u_nvhs_7>;

			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",

				    "p2u-5", "p2u-6", "p2u-7";

		};

	};



	gpio-keys {
@@ -2145,57 +2196,6 @@ 
		label = "NVIDIA Jetson AGX Orin APE";

	};



	pcie@14100000 {

		status = "okay";



		vddio-pex-ctl-supply = <&vdd_1v8_ao>;



		phys = <&p2u_hsio_3>;

		phy-names = "p2u-0";

	};



	pcie@14160000 {

		status = "okay";



		vddio-pex-ctl-supply = <&vdd_1v8_ao>;



		phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,

		       <&p2u_hsio_7>;

		phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";

	};



	pcie@141a0000 {

		status = "okay";



		vddio-pex-ctl-supply = <&vdd_1v8_ls>;

		vpcie3v3-supply = <&vdd_3v3_pcie>;

		vpcie12v-supply = <&vdd_12v_pcie>;



		phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,

		       <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,

		       <&p2u_nvhs_6>, <&p2u_nvhs_7>;

		phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",

			    "p2u-5", "p2u-6", "p2u-7";

	};



	pcie-ep@141a0000 {

		status = "disabled";



		vddio-pex-ctl-supply = <&vdd_1v8_ls>;



		reset-gpios = <&gpio TEGRA234_MAIN_GPIO(AF, 1) GPIO_ACTIVE_LOW>;



		nvidia,refclk-select-gpios = <&gpio_aon

					      TEGRA234_AON_GPIO(AA, 4)

					      GPIO_ACTIVE_HIGH>;



		phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,

		       <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,

		       <&p2u_nvhs_6>, <&p2u_nvhs_7>;

		phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",

			    "p2u-5", "p2u-6", "p2u-7";

	};



	pwm-fan {

		compatible = "pwm-fan";

		pwms = <&pwm3 0 45334>;

arch/arm64/boot/dts/nvidia/tegra234.dtsi

+767 −763

File changed.

Preview size limit exceeded, changes collapsed.