Commit 280c4447 authored by Chih-Kang Chang's avatar Chih-Kang Chang Committed by Kalle Valo
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wifi: rtw89: config EDCCA threshold during scan to prevent TX failed



Need to configure EDCCA threshold to default value before scan, and recall
original value after scan to prevent probe request can't be sent out.

Signed-off-by: default avatarChih-Kang Chang <gary.chang@realtek.com>
Signed-off-by: default avatarPing-Ke Shih <pkshih@realtek.com>
Signed-off-by: default avatarKalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20230322060238.43922-1-pkshih@realtek.com
parent 40711486
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+2 −0
Original line number Diff line number Diff line
@@ -3264,6 +3264,7 @@ void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
	rtw89_btc_ntfy_scan_start(rtwdev, RTW89_PHY_0, chan->band_type);
	rtw89_chip_rfk_scan(rtwdev, true);
	rtw89_hci_recalc_int_mit(rtwdev);
	rtw89_phy_config_edcca(rtwdev, true);

	rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, mac_addr);
}
@@ -3281,6 +3282,7 @@ void rtw89_core_scan_complete(struct rtw89_dev *rtwdev,

	rtw89_chip_rfk_scan(rtwdev, false);
	rtw89_btc_ntfy_scan_finish(rtwdev, RTW89_PHY_0);
	rtw89_phy_config_edcca(rtwdev, false);

	rtwdev->scanning = false;
	rtwdev->dig.bypass_dig = true;
+3 −0
Original line number Diff line number Diff line
@@ -3152,6 +3152,7 @@ struct rtw89_chip_info {
	const struct rtw89_rrsr_cfgs *rrsr_cfgs;
	u32 bss_clr_map_reg;
	u32 dma_ch_mask;
	u32 edcca_lvl_reg;
	const struct wiphy_wowlan_support *wowlan_stub;
};

@@ -3363,6 +3364,8 @@ struct rtw89_hal {

	bool entity_active;
	enum rtw89_entity_mode entity_mode;

	u32 edcca_bak;
};

#define RTW89_MAX_MAC_ID_NUM 128
+19 −0
Original line number Diff line number Diff line
@@ -4366,3 +4366,22 @@ void rtw89_decode_chan_idx(struct rtw89_dev *rtwdev, u8 chan_idx,
	*ch = rtw89_ch_base_table[idx] + (offset << 1);
}
EXPORT_SYMBOL(rtw89_decode_chan_idx);

#define EDCCA_DEFAULT 249
void rtw89_phy_config_edcca(struct rtw89_dev *rtwdev, bool scan)
{
	u32 reg = rtwdev->chip->edcca_lvl_reg;
	struct rtw89_hal *hal = &rtwdev->hal;
	u32 val;

	if (scan) {
		hal->edcca_bak = rtw89_phy_read32(rtwdev, reg);
		val = hal->edcca_bak;
		u32p_replace_bits(&val, EDCCA_DEFAULT, B_SEG0R_EDCCA_LVL_A_MSK);
		u32p_replace_bits(&val, EDCCA_DEFAULT, B_SEG0R_EDCCA_LVL_P_MSK);
		u32p_replace_bits(&val, EDCCA_DEFAULT, B_SEG0R_PPDU_LVL_MSK);
		rtw89_phy_write32(rtwdev, reg, val);
	} else {
		rtw89_phy_write32(rtwdev, reg, hal->edcca_bak);
	}
}
+1 −0
Original line number Diff line number Diff line
@@ -558,5 +558,6 @@ void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev);
u8 rtw89_encode_chan_idx(struct rtw89_dev *rtwdev, u8 central_ch, u8 band);
void rtw89_decode_chan_idx(struct rtw89_dev *rtwdev, u8 chan_idx,
			   u8 *ch, enum nl80211_band *band);
void rtw89_phy_config_edcca(struct rtw89_dev *rtwdev, bool scan);

#endif
+5 −0
Original line number Diff line number Diff line
@@ -4280,6 +4280,11 @@
#define B_PKT_POP_EN BIT(8)
#define R_SEG0R_PD 0x481C
#define R_SEG0R_PD_V1 0x4860
#define R_SEG0R_EDCCA_LVL 0x4840
#define R_SEG0R_EDCCA_LVL_V1 0x4884
#define B_SEG0R_PPDU_LVL_MSK GENMASK(31, 24)
#define B_SEG0R_EDCCA_LVL_P_MSK GENMASK(15, 8)
#define B_SEG0R_EDCCA_LVL_A_MSK GENMASK(7, 0)
#define B_SEG0R_PD_SPATIAL_REUSE_EN_MSK_V1 BIT(30)
#define B_SEG0R_PD_SPATIAL_REUSE_EN_MSK BIT(29)
#define B_SEG0R_PD_LOWER_BOUND_MSK GENMASK(10, 6)
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