Commit 27de8d59 authored by Rafael J. Wysocki's avatar Rafael J. Wysocki
Browse files

Merge branch 'cpufreq/arm/linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm 

Pull more ARM cpufreq changes for v5.15-rc1 from Viresh Kumar:

"This adds a new cpufreq driver for Mediatek, which had been going
 through reviews since last one year."

* 'cpufreq/arm/linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm:
  cpufreq: mediatek-hw: Add support for CPUFREQ HW
  cpufreq: Add of_perf_domain_get_sharing_cpumask
  dt-bindings: cpufreq: add bindings for MediaTek cpufreq HW
parents dd7c46d6 4855e26b

Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/cpufreq/cpufreq-mediatek-hw.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: MediaTek's CPUFREQ Bindings



maintainers:

  - Hector Yuan <hector.yuan@mediatek.com>



description:

  CPUFREQ HW is a hardware engine used by MediaTek SoCs to

  manage frequency in hardware. It is capable of controlling

  frequency for multiple clusters.



properties:

  compatible:

    const: mediatek,cpufreq-hw



  reg:

    minItems: 1

    maxItems: 2

    description:

      Addresses and sizes for the memory of the HW bases in

      each frequency domain. Each entry corresponds to

      a register bank for each frequency domain present.



  "#performance-domain-cells":

    description:

      Number of cells in a performance domain specifier.

      Set const to 1 here for nodes providing multiple

      performance domains.

    const: 1



required:

  - compatible

  - reg

  - "#performance-domain-cells"



additionalProperties: false



examples:

  - |

    cpus {

            #address-cells = <1>;

            #size-cells = <0>;



            cpu0: cpu@0 {

                device_type = "cpu";

                compatible = "arm,cortex-a55";

                enable-method = "psci";

                performance-domains = <&performance 0>;

                reg = <0x000>;

            };

    };



    /* ... */



    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        performance: performance-controller@11bc00 {

            compatible = "mediatek,cpufreq-hw";

            reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;



            #performance-domain-cells = <1>;

        };

    };

drivers/cpufreq/Kconfig.arm

+12 −0
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@@ -133,6 +133,18 @@ config ARM_MEDIATEK_CPUFREQ 
	help

	  This adds the CPUFreq driver support for MediaTek SoCs.



config ARM_MEDIATEK_CPUFREQ_HW

	tristate "MediaTek CPUFreq HW driver"

	depends on ARCH_MEDIATEK || COMPILE_TEST

	default m

	help

	  Support for the CPUFreq HW driver.

	  Some MediaTek chipsets have a HW engine to offload the steps

	  necessary for changing the frequency of the CPUs. Firmware loaded

	  in this engine exposes a programming interface to the OS.

	  The driver implements the cpufreq interface for this HW engine.

	  Say Y if you want to support CPUFreq HW.



config ARM_OMAP2PLUS_CPUFREQ

	bool "TI OMAP2+"

	depends on ARCH_OMAP2PLUS

drivers/cpufreq/Makefile

+1 −0
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@@ -56,6 +56,7 @@ obj-$(CONFIG_ARM_IMX6Q_CPUFREQ) += imx6q-cpufreq.o 
obj-$(CONFIG_ARM_IMX_CPUFREQ_DT)	+= imx-cpufreq-dt.o

obj-$(CONFIG_ARM_KIRKWOOD_CPUFREQ)	+= kirkwood-cpufreq.o

obj-$(CONFIG_ARM_MEDIATEK_CPUFREQ)	+= mediatek-cpufreq.o

obj-$(CONFIG_ARM_MEDIATEK_CPUFREQ_HW)	+= mediatek-cpufreq-hw.o

obj-$(CONFIG_MACH_MVEBU_V7)		+= mvebu-cpufreq.o

obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ)	+= omap-cpufreq.o

obj-$(CONFIG_ARM_PXA2xx_CPUFREQ)	+= pxa2xx-cpufreq.o

drivers/cpufreq/mediatek-cpufreq-hw.c

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// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (c) 2020 MediaTek Inc.

 */



#include <linux/bitfield.h>

#include <linux/cpufreq.h>

#include <linux/energy_model.h>

#include <linux/init.h>

#include <linux/iopoll.h>

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/of_address.h>

#include <linux/of_platform.h>

#include <linux/slab.h>



#define LUT_MAX_ENTRIES			32U

#define LUT_FREQ			GENMASK(11, 0)

#define LUT_ROW_SIZE			0x4

#define CPUFREQ_HW_STATUS		BIT(0)

#define SVS_HW_STATUS			BIT(1)

#define POLL_USEC			1000

#define TIMEOUT_USEC			300000



enum {

	REG_FREQ_LUT_TABLE,

	REG_FREQ_ENABLE,

	REG_FREQ_PERF_STATE,

	REG_FREQ_HW_STATE,

	REG_EM_POWER_TBL,

	REG_FREQ_LATENCY,



	REG_ARRAY_SIZE,

};



struct mtk_cpufreq_data {

	struct cpufreq_frequency_table *table;

	void __iomem *reg_bases[REG_ARRAY_SIZE];

	int nr_opp;

};



static const u16 cpufreq_mtk_offsets[REG_ARRAY_SIZE] = {

	[REG_FREQ_LUT_TABLE]	= 0x0,

	[REG_FREQ_ENABLE]	= 0x84,

	[REG_FREQ_PERF_STATE]	= 0x88,

	[REG_FREQ_HW_STATE]	= 0x8c,

	[REG_EM_POWER_TBL]	= 0x90,

	[REG_FREQ_LATENCY]	= 0x110,

};



static int __maybe_unused

mtk_cpufreq_get_cpu_power(unsigned long *mW,

			  unsigned long *KHz, struct device *cpu_dev)

{

	struct mtk_cpufreq_data *data;

	struct cpufreq_policy *policy;

	int i;



	policy = cpufreq_cpu_get_raw(cpu_dev->id);

	if (!policy)

		return 0;



	data = policy->driver_data;



	for (i = 0; i < data->nr_opp; i++) {

		if (data->table[i].frequency < *KHz)

			break;

	}

	i--;



	*KHz = data->table[i].frequency;

	*mW = readl_relaxed(data->reg_bases[REG_EM_POWER_TBL] +

			    i * LUT_ROW_SIZE) / 1000;



	return 0;

}



static int mtk_cpufreq_hw_target_index(struct cpufreq_policy *policy,

				       unsigned int index)

{

	struct mtk_cpufreq_data *data = policy->driver_data;



	writel_relaxed(index, data->reg_bases[REG_FREQ_PERF_STATE]);



	return 0;

}



static unsigned int mtk_cpufreq_hw_get(unsigned int cpu)

{

	struct mtk_cpufreq_data *data;

	struct cpufreq_policy *policy;

	unsigned int index;



	policy = cpufreq_cpu_get_raw(cpu);

	if (!policy)

		return 0;



	data = policy->driver_data;



	index = readl_relaxed(data->reg_bases[REG_FREQ_PERF_STATE]);

	index = min(index, LUT_MAX_ENTRIES - 1);



	return data->table[index].frequency;

}



static unsigned int mtk_cpufreq_hw_fast_switch(struct cpufreq_policy *policy,

					       unsigned int target_freq)

{

	struct mtk_cpufreq_data *data = policy->driver_data;

	unsigned int index;



	index = cpufreq_table_find_index_dl(policy, target_freq);



	writel_relaxed(index, data->reg_bases[REG_FREQ_PERF_STATE]);



	return policy->freq_table[index].frequency;

}



static int mtk_cpu_create_freq_table(struct platform_device *pdev,

				     struct mtk_cpufreq_data *data)

{

	struct device *dev = &pdev->dev;

	u32 temp, i, freq, prev_freq = 0;

	void __iomem *base_table;



	data->table = devm_kcalloc(dev, LUT_MAX_ENTRIES + 1,

				   sizeof(*data->table), GFP_KERNEL);

	if (!data->table)

		return -ENOMEM;



	base_table = data->reg_bases[REG_FREQ_LUT_TABLE];



	for (i = 0; i < LUT_MAX_ENTRIES; i++) {

		temp = readl_relaxed(base_table + (i * LUT_ROW_SIZE));

		freq = FIELD_GET(LUT_FREQ, temp) * 1000;



		if (freq == prev_freq)

			break;



		data->table[i].frequency = freq;



		dev_dbg(dev, "index=%d freq=%d\n", i, data->table[i].frequency);



		prev_freq = freq;

	}



	data->table[i].frequency = CPUFREQ_TABLE_END;

	data->nr_opp = i;



	return 0;

}



static int mtk_cpu_resources_init(struct platform_device *pdev,

				  struct cpufreq_policy *policy,

				  const u16 *offsets)

{

	struct mtk_cpufreq_data *data;

	struct device *dev = &pdev->dev;

	void __iomem *base;

	int ret, i;

	int index;



	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);

	if (!data)

		return -ENOMEM;



	index = of_perf_domain_get_sharing_cpumask(policy->cpu, "performance-domains",

						   "#performance-domain-cells",

						   policy->cpus);

	if (index < 0)

		return index;



	base = devm_platform_ioremap_resource(pdev, index);

	if (IS_ERR(base))

		return PTR_ERR(base);



	for (i = REG_FREQ_LUT_TABLE; i < REG_ARRAY_SIZE; i++)

		data->reg_bases[i] = base + offsets[i];



	ret = mtk_cpu_create_freq_table(pdev, data);

	if (ret) {

		dev_info(dev, "Domain-%d failed to create freq table\n", index);

		return ret;

	}



	policy->freq_table = data->table;

	policy->driver_data = data;



	return 0;

}



static int mtk_cpufreq_hw_cpu_init(struct cpufreq_policy *policy)

{

	struct platform_device *pdev = cpufreq_get_driver_data();

	int sig, pwr_hw = CPUFREQ_HW_STATUS | SVS_HW_STATUS;

	struct mtk_cpufreq_data *data;

	unsigned int latency;

	int ret;



	/* Get the bases of cpufreq for domains */

	ret = mtk_cpu_resources_init(pdev, policy, platform_get_drvdata(pdev));

	if (ret) {

		dev_info(&pdev->dev, "CPUFreq resource init failed\n");

		return ret;

	}



	data = policy->driver_data;



	latency = readl_relaxed(data->reg_bases[REG_FREQ_LATENCY]) * 1000;

	if (!latency)

		latency = CPUFREQ_ETERNAL;



	policy->cpuinfo.transition_latency = latency;

	policy->fast_switch_possible = true;



	/* HW should be in enabled state to proceed now */

	writel_relaxed(0x1, data->reg_bases[REG_FREQ_ENABLE]);

	if (readl_poll_timeout(data->reg_bases[REG_FREQ_HW_STATE], sig,

			       (sig & pwr_hw) == pwr_hw, POLL_USEC,

			       TIMEOUT_USEC)) {

		if (!(sig & CPUFREQ_HW_STATUS)) {

			pr_info("cpufreq hardware of CPU%d is not enabled\n",

				policy->cpu);

			return -ENODEV;

		}



		pr_info("SVS of CPU%d is not enabled\n", policy->cpu);

	}



	return 0;

}



static int mtk_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy)

{

	struct mtk_cpufreq_data *data = policy->driver_data;



	/* HW should be in paused state now */

	writel_relaxed(0x0, data->reg_bases[REG_FREQ_ENABLE]);



	return 0;

}



static void mtk_cpufreq_register_em(struct cpufreq_policy *policy)

{

	struct em_data_callback em_cb = EM_DATA_CB(mtk_cpufreq_get_cpu_power);

	struct mtk_cpufreq_data *data = policy->driver_data;



	em_dev_register_perf_domain(get_cpu_device(policy->cpu), data->nr_opp,

				    &em_cb, policy->cpus, true);

}



static struct cpufreq_driver cpufreq_mtk_hw_driver = {

	.flags		= CPUFREQ_NEED_INITIAL_FREQ_CHECK |

			  CPUFREQ_HAVE_GOVERNOR_PER_POLICY |

			  CPUFREQ_IS_COOLING_DEV,

	.verify		= cpufreq_generic_frequency_table_verify,

	.target_index	= mtk_cpufreq_hw_target_index,

	.get		= mtk_cpufreq_hw_get,

	.init		= mtk_cpufreq_hw_cpu_init,

	.exit		= mtk_cpufreq_hw_cpu_exit,

	.register_em	= mtk_cpufreq_register_em,

	.fast_switch	= mtk_cpufreq_hw_fast_switch,

	.name		= "mtk-cpufreq-hw",

	.attr		= cpufreq_generic_attr,

};



static int mtk_cpufreq_hw_driver_probe(struct platform_device *pdev)

{

	const void *data;

	int ret;



	data = of_device_get_match_data(&pdev->dev);

	if (!data)

		return -EINVAL;



	platform_set_drvdata(pdev, (void *) data);

	cpufreq_mtk_hw_driver.driver_data = pdev;



	ret = cpufreq_register_driver(&cpufreq_mtk_hw_driver);

	if (ret)

		dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n");



	return ret;

}



static int mtk_cpufreq_hw_driver_remove(struct platform_device *pdev)

{

	return cpufreq_unregister_driver(&cpufreq_mtk_hw_driver);

}



static const struct of_device_id mtk_cpufreq_hw_match[] = {

	{ .compatible = "mediatek,cpufreq-hw", .data = &cpufreq_mtk_offsets },

	{}

};



static struct platform_driver mtk_cpufreq_hw_driver = {

	.probe = mtk_cpufreq_hw_driver_probe,

	.remove = mtk_cpufreq_hw_driver_remove,

	.driver = {

		.name = "mtk-cpufreq-hw",

		.of_match_table = mtk_cpufreq_hw_match,

	},

};

module_platform_driver(mtk_cpufreq_hw_driver);



MODULE_AUTHOR("Hector Yuan <hector.yuan@mediatek.com>");

MODULE_DESCRIPTION("Mediatek cpufreq-hw driver");

MODULE_LICENSE("GPL v2");

include/linux/cpufreq.h

+57 −1
Original line number Diff line number Diff line
@@ -14,6 +14,8 @@ 
#include <linux/completion.h>

#include <linux/kobject.h>

#include <linux/notifier.h>

#include <linux/of.h>

#include <linux/of_device.h>

#include <linux/pm_opp.h>

#include <linux/pm_qos.h>

#include <linux/spinlock.h>
@@ -1000,6 +1002,55 @@ static inline int cpufreq_table_count_valid_entries(const struct cpufreq_policy 


	return count;

}



static inline int parse_perf_domain(int cpu, const char *list_name,

				    const char *cell_name)

{

	struct device_node *cpu_np;

	struct of_phandle_args args;

	int ret;



	cpu_np = of_cpu_device_node_get(cpu);

	if (!cpu_np)

		return -ENODEV;



	ret = of_parse_phandle_with_args(cpu_np, list_name, cell_name, 0,

					 &args);

	if (ret < 0)

		return ret;



	of_node_put(cpu_np);



	return args.args[0];

}



static inline int of_perf_domain_get_sharing_cpumask(int pcpu, const char *list_name,

						     const char *cell_name, struct cpumask *cpumask)

{

	int target_idx;

	int cpu, ret;



	ret = parse_perf_domain(pcpu, list_name, cell_name);

	if (ret < 0)

		return ret;



	target_idx = ret;

	cpumask_set_cpu(pcpu, cpumask);



	for_each_possible_cpu(cpu) {

		if (cpu == pcpu)

			continue;



		ret = parse_perf_domain(pcpu, list_name, cell_name);

		if (ret < 0)

			continue;



		if (target_idx == ret)

			cpumask_set_cpu(cpu, cpumask);

	}



	return target_idx;

}

#else

static inline int cpufreq_boost_trigger_state(int state)

{
@@ -1019,6 +1070,12 @@ static inline bool policy_has_boost_freq(struct cpufreq_policy *policy) 
{

	return false;

}



static inline int of_perf_domain_get_sharing_cpumask(int pcpu, const char *list_name,

						     const char *cell_name, struct cpumask *cpumask)

{

	return -EOPNOTSUPP;

}

#endif



#if defined(CONFIG_ENERGY_MODEL) && defined(CONFIG_CPU_FREQ_GOV_SCHEDUTIL)
@@ -1040,7 +1097,6 @@ void arch_set_freq_scale(const struct cpumask *cpus, 
{

}

#endif



/* the following are really really optional */

extern struct freq_attr cpufreq_freq_attr_scaling_available_freqs;

extern struct freq_attr cpufreq_freq_attr_scaling_boost_freqs;