Commit 27cb06af authored by Helge Deller's avatar Helge Deller Committed by openeuler-sync-bot
Browse files

parisc/unaligned: Rewrite 32-bit inline assembly of emulate_sth() 

mainline inclusion
from mainline-v5.18-rc1
commit 3029ce31
category: bugfix
bugzilla: https://gitee.com/src-openeuler/kernel/issues/I9E2GP
CVE: CVE-2024-26706

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=3029ce31af158631feffdab067e99bb22b7369c4



--------------------------------

Convert to use real temp variables instead of clobbering processor
registers.

Signed-off-by: default avatarHelge Deller <deller@gmx.de>
Signed-off-by: default avatarCheng Yu <serein.chengyu@huawei.com>
(cherry picked from commit 244aff3b)
parent a4cbfbba

arch/parisc/kernel/unaligned.c

+7 −8
Original line number Diff line number Diff line
@@ -234,7 +234,7 @@ static int emulate_ldd(struct pt_regs *regs, int toreg, int flop) 


static int emulate_sth(struct pt_regs *regs, int frreg)

{

	unsigned long val = regs->gr[frreg];

	unsigned long val = regs->gr[frreg], temp1;

	ASM_EXCEPTIONTABLE_VAR(ret);



	if (!frreg)
@@ -244,16 +244,15 @@ static int emulate_sth(struct pt_regs *regs, int frreg) 
		val, regs->isr, regs->ior);



	__asm__ __volatile__ (

"	mtsp %3, %%sr1\n"

"	extrw,u %1, 23, 8, %%r19\n"

"1:	stb %1, 1(%%sr1, %2)\n"

"2:	stb %%r19, 0(%%sr1, %2)\n"

"	mtsp %4, %%sr1\n"

"	extrw,u %2, 23, 8, %1\n"

"1:	stb %1, 0(%%sr1, %3)\n"

"2:	stb %2, 1(%%sr1, %3)\n"

"3:	\n"

	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b)

	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b)

	: "+r" (ret)

	: "r" (val), "r" (regs->ior), "r" (regs->isr)

	: "r19" );

	: "+r" (ret), "=&r" (temp1)

	: "r" (val), "r" (regs->ior), "r" (regs->isr) );



	return ret;

}